A new configuration of high gain circularly polarized microstrip antenna with a diagonal short and its analysis using boundary element method with a radiation load are presented. The center of a radiating patch is shorted with a 45-degree diagonal offset for not only obtaining a high gain but exciting a circular polarization. This configuration leads to achieving high gain with keeping a very low profile configuration. Boundary element method with radiation load which takes into account the effect of radiation loss is employed to analyze this complicated configuration. The radiation load, which is very important when boundary element method is applied to antenna analyses, can be obtained from radiation admittance using recurring technique, so that the accuracy of the antenna characteristic calculations can be improved. This antenna was designed and tested in the L-band and good characteristics, axial ratios and radiation patterns, have been verified.

New functional surface tunnel transistors (STTs) with multiple interband-tunnel-junctions in a symmetric source-to-drain structure are proposed to reduce the number of fabrication steps and to increase functionality. These devices have p+/n+ interband tunnel junctions in series between a p+ source and a p+ drain through n+ channels. We successfully fabricated GaAs-based multiple-junction STTs (MJ-STTs) using molecular-beam epitaxy regrowth. This fabrication method eliminates the need for two of the photo-masks in the conventional process for asymmetric planar STTs. In the preliminary experiments using multiple-junction p+/n+ diodes, we found that the peak-voltage increment in negative-differential-resistance (NDR) characteristics due to the reverse-biased tunnel junction in negligible, while the first-peak voltage is roughly proportional to the number of forward-biased tunnel junctions. Moreover, the number of NDR characteristics are completely determined by the number of tunnel junctions. The fabricated STTs with multiple junctions, up to eight junctions, exhibited clear transistor operation with multiple NDR characteristics, which were symmetric with the drain bias. These results indicate that any number of gate-controlled NDR characteristics can be realized in MJ-STTs by using an appropriate number of tunnel junctions in series. In addition, as an example of a functional circuit using MJ-STTs, we implemented a tri-stable circuit with a four-junction STT and a load resistor connected in series. The tri-stable operation was confirmed by applying a combination of a reset pulse and a set pulse for each stable point.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

This paper describes influence of the relaxation current in BaxSr(1-x)TiO3 (BST) thin films on dynamic random access memory (DRAM) operation. The relaxation current is a transient content of dielectric leakage currents. In BST thin films (expected to be a cell capacitor dielectric in 256 Mb DRAM and beyond), the relaxation current often displays the power law behavior I(t)t-1. This leads to the singularity near the time zero. When one attempts to evaluate precisely the influence of this leakage on DRAM operation, the behavior should be estimated on a time-dependent bias. However, such a singular behavior makes analysis based on a linear response difficult. In this analysis, we start by assuming that the behavior of the relaxation current can be modeled as a linear equivalent circuit. We also assume that the relaxation current follows the power law, I(t)t-1 for 1 ns

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

This paper describes a guiding principle for designing functional single-electron tunneling (SET) circuitsthat is a way to elicit the potential functions of a given SET circuit by using as a guiding tool the SET circuit stability diagram. A stability diagram is a map that depicts the stable regions of a SET circuit based on the circuit's variable coordinates. By scrutinizing the diagram, we can infer all the potential functions that can be obtained from a circuit configuration. As an example, we take up a well-known SET-inverter circuit and uncover its latent functions by studying the circuit configuration, based on its stability diagram. We can produce various functions, e.g., step-inverter, Schmidt-trigger, memory cell, literal, and stochastic-neuron functions. The last function makes good use of the inherent stochastic nature of single-electron tunneling, and can be applied to Boltzmann-machine neural network systems.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

A novel learning algorithm for a neural network LSI which has low resolution synapse weights is proposed. Following a brief discussion of the synapse weight adaptation mechanism in the gradient descent scheme, we propose a way of achieving relaxation from the influence of discretized weight. Restriction of the number of synapses to be updated in one learning iteration is effective to relax the influence. Simulation results support the effectiveness of this learning algorithm. Low resolution synapses will be practical to realize large-scale neural network LSIs.

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.

This paper presents the several bifurcation phenomena of harmonic oscillations occurred in nonlinear three-phase circuit. The circuit consists of delta-connected nonlinear inductors, capacitors and three-phase symmetrical voltage sources. We analyze the bifurcations of the oscillations by the homotopy method. Additionally, we confirm the bifurcation phenomena by real experiments. Furthermore, we reveal the effect of nonlinear couplings of inductors by the comparison of harmonic oscillations in a single-phase circuit.

The Telecommunications Management Network (TMN) is a major focus of telecommunications operations work in the 1990s. New telecommunication equipment is required to conform to the TMN standards. In the TMN, a network element is managed as a set of Managed Objects (MOs). The MO program has to be executed in a muiltithreaded, parallel environment for a quick response; therefore, concurrency control is a key issue for developing an MO program. This paper proposes a formal definition to specify data for concurrency control to improve the correctness and reusability of the specification. The definition is based on a Generic Relationship Model (GRM). By using the formalized definition and developing an algorithm to translate the definition into executable code, concurrency control is performed without coding. After describing the algorithm used to perform concurrency control, this paper discusses a three-layer concurrency control architecture to accommodate this framework efficiently.

A clock-feedthrough (CFT) compensation technique using a dummy cell is valid when the CFT current from a switched-current (SI) memory cell is signal-independent. Based on this idea, a SI dummy cell appropriate for the S2I cell is developed. Simulations show that the CFT rejection ratio as high as 60dB is attainable over the temperature range from -30 to 80 with this architecture. The CFT-compensated SI cell proposed here is, therefore, quite usuful for high-accuracy, current-mode signal processing.

A high performance, high-swing CMOS cascode current mirror operating with 1V power supply voltage and using standard CMOS technology is presented. The present circuit employs PMOS source-coupled pair as voltage level shifter to reduce the power supply voltage requirement. The additional advantages of the use of the source-coupled pair are the improved output resistance and the automatic adaptive biasing, thereby enabling the high-swing of output terminal, when used in the cascode configuration. An analytical discussion of the circuit is carried out and the results are confirmed by SPICE simulation. SPICE simulation results show that the input voltage requirement is 370mV and the minimum output voltage requirement is 273mV at the maximum input current of 40µA, whose requirements decrease with decreasing input currens. The output resistance is shown to be greater than 4MΩ at the maximum output current of 40µA, which increases with decreasing output currents. The -3dB bandwidth is shown to be greater than 400MHz and the total harmonic distortion better than -54.34dB at 100kHz at the maximum peak-to-peak input current swing of 40µA. The present circuit will be useful for the low voltage, low power, high-performance mixed analog/digital signal processing.

As enterprises use ATM networks for their private networks and as these private networks use public ATM networks for wide area communication, the need for the customers to be able to manage both private and public networks is increasing. Currently, some standardization work is being done towards providing this capability to customers. In this paper, we propose a new customer network management (CNM) system architecture for the management of both private and public ATM networks in a uniform way. The particular features of the proposed architecture lies in the efficient support of the complex hierarchical TMN manager-agent relationships at M3 and M4 interfaces, and the support of SNMP and CMIP integration. The TMN hierarchical many-to-many manager-agent relationships are realized by the utilization of a CORBA-based Shared Management Knowledge (SMK) system. We have implemented a prototype of ATM CNM system, and measured the performance for the demonstration of the suitability of the proposed architecture.

Calculation Nv(x) of complex order v numerically, we must calculate Df{JN+ε(x)}. When Df{JN+ε(x)} is calculated by the recurrence method, this letter will analyze the error of Df{JN+ε(x)}, and will determine the optimum number of recurrences.

Dynamic Term Rewriting Calculus is a new computation model proposed by the authors for the purpose of formal description and verification of algorithms treating Term Rewriting Systems. The computation of DTRC is basically term rewriting. The characteristic features of DTRC are dynamic change of rewriting rules during computation and hierarchical declaration of not only function symbols and variables but also rewriting rules. These features allow us to program metacomputation of TRSs in DTRC, that is , we can implement in DTRC in a natural way those algorithms which manipulate term rewriting systems as well as those procedures which verify such algorithms. In this paper, we give a formal description of DTRC. We then show some results on confluence property of DTRC.

In bandlimited QPSK and QAM transmission systems, phase jitter occurs in the output of a carrier recovery circuit that uses a fourth-power multiplier. To analyze the phase jitter, an exact expression was derived for the autocorrelation function and power spectral density for the case in which bandlimited Gaussian noise and a QPSK or QAM signal with random modulation and arbitrary waveform are simultaneously applied to the fourth-power multiplier. Using this expression, the rms phase jitter of the recovered carrier in root-cosine-rolloff transmission systems for QPSK, 16QAM, 64QAM and 256QAM was calculated. It was shown that the conventional theories for rectangular waveforms are special cases of our theory.

Silica-based planar lightwave circuits (PLCs) are reviewed in terms of WDM applications. Four types of basic multiplexer are described and compared. Some topical applications of these multiplexers are introduced with their WDM systems. We conclude that because of these various applications, silica-based PLCs will play an important role in future WDM systems.