When we use a telephone-handset, the frequency response of the telephone-earphone becomes degraded because of the leak through the slit between the ear and the earphone. Consequently, it is very important to establish the design method of the telephone-handset which reduces the effect of leak. No one has tried to design the telephone-handset to reduce the effect. We are the only ones to have proposed an automatic design method by nonlinear optimization techniques. However, this method gives only one set of the acoustic parameters aiming at a certain specific target frequency response, and therefore lacks flexibility in the actual design problem. On the other hand, the design method proposed in this paper, which uses Monte-Carlo method, gives an infinite number of sets of acoustic parameters that realize infinite frequency responses within the target allowable region. As these infinite number of sets become directly the design ranges of acoustic parameters, the proposed method has the flexibility that any set of the acoustic parameters belonging to the design ranges guarantees the corresponding response to be within the target allowable region, and at the same time reduces the effect of leak. This flexibility is advantageous to the actual design problem.

A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70.

We have fabricated a new analog memory for integrated artificial neural networks. Several attempts have been made to develop a linear characteristics of floating-gate analog memorys with feedback circuits. The learning chip has to have a large number of learning control circuit. In this paper, we propose a new analog memory SDAM with three cascaded TFTs. The new analog memory has a simple design, a small area occupancy, a fast switching speed and an accurate linearity. To improve accurate linearity, we propose a new chargetransfer process. The device has a tunnel junction (poly-Si/poly-Si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating-gate MOSFET. The diffusion of the charges injected through the tunnel junction are controlled by a source follower operation of a thin film transistor (TFT). The proposed operation is possible that the amounts of transferred charges are constant independent of the charges in storage capacitor.

A broadband rhombic loop antenna is introduced to radiate a circularly polarized wave. This antenna has a single feed and is located above a ground plane. The perimeter of the loop is typically about 1.3 wavelength. One gap is made on the loop to produce a traveling wave distribution of current. Antenna characteristics are calculated by the method of moments and compared with the measured data. By adjusting a perimeter and a gap position of the loop, circular polarization is obtained. In addition, with the appropriate vertex angle of the rhombus, the bandwidth of about 20% for the axial ratio (2dB) is attained and the possibility of controlling the input impedance is found. Finally, it is observed that sense of circular polarization can be changed easily from left-hand to right-hand, and vice versa by switching one gap position to the other on the rhombic loop.

A CMOS fully balanced current-mode filter is presented. A fully balanced current-mode integrator which is the basic building block is implemented by adding a very simple common-mode-rejection mechanism to fully differential one. The fully balanced operation can eliminate even order distortion, which is one of the drawbacks in previous continuous current-mode filter. Moreover, the additional circuit can work as not only common-mode-rejection mechanism but also Q-tuning circuit which compensates lossy elements due to finite output impedance of MOS FET. A prototype fifth-order low-pass lad-der filter designed in a standard digital 0.8µm CMOS process achieved a cut-off frequency (fC) of 100MHz; fC was tunable from 75MHz to 120MHz by varying a reference bias current from 50µA to 150µA. Using a single 3V power supply with a nominal reference current of 100µA, power dissipation per one pole is 30mW. The active filter area was 0.011mm2/pole and total harmonic distortion (THD) was 0.73 [%] at 80MHz, 80µA amplitude signal. Furthermore, by adjusting two bias currents, on chip automatic both frequency and Q controls are easily implemented by typical tuning systems, for example master-slave tuning systems [1].

In general, a learning machine will behave better as the number of training examples increases. It is important to know how fast and how well the behavior is improved. The average prediction error, the average of the probability that the trained machine mispredicts the output signal, is one of the most popular criteria to see the behavior. However, it is not easy to evaluate the average prediction error even in the simplest case, that is, the linear dichotomy (perceptron) case. When a continuous deterministic dichotomy machine is trained by t examples of input-output pairs produced from a realizable teacher, these examples limits the region of the parameter space which includes the true parameter. Any parameter in the region can explain the input-output behaviors of the examples. Such a region, celled the admissible region, forms in general a (curved) polyhedron in the parameter space, and it becomes smaller and smaller as the number of examples increases. The present paper studies the shape and volume of the admissible region. We use the stochastic geometrical approach to this problem. We have studied the stochastic geometrical features of the admissible region using the fact that it is dual to the convex hull the examples make in the example space. Since the admissible region is related to the average prediction error of the linear dichotomy, we derived the new upper and lower bounds of the average prediction error.

The data retention characteristics for Flash EEPROM degrade after a large number of write and erase cycles due to the increase of the tunnel oxide leakage current. This paper proposes a new write/erase method which uses a reverse polarity pulse after each erase pulse. By using this method, the leakage current can be suppressed. As a result, the read disturb time after 105cycles write/erase operation is more than 10 times longer in comparison with that of the conventional method. Moreover, using this method, the endurance cycle dependence of the threshold voltage after write and erase operation is also drastically improved.

The effects of α-particle-induced parasitic bipolar current on soft errors in submicron 6-transistor SOI SRAMs were numericaly studied. It was shown that the bipolar current induces soft errors and that there exists a critical quantity which determines the soft error occurrence in the SOI SRAMs. Simulated soft error rates were in the same order as those for bulk SRAMs.

In this paper, we show that the conventional BCH codes can be better than the AG codes when the number of check symbols is relatively small. More precisely, we consider an AG code on Cab whose number of check symbols is less than min {g+a, n-g}, where n and g denote the code length and the genus of the curve, respectively. It is shown that there always exists an extended BCH code, (i) which has the same designed distance as the Feng-Rao designed distance of the AG code and the code length and the rate greater than those of the AG code, or (ii) which has the same number of check symbols as that of the AG code, the designed distance not less than that of the AG code and the code length longer than that of the AG code.

Discrete-time chaotic circuits realizing a tent map and a Bernoulli map are synthesized using switched-current (SI) techniques. For these proposed circuits, simulations are performed concerning the return maps and bifurcation trees. The theoretical analysis is carried out to predict the bifurcation tree under the existence of the nonidealities in the return map. This analysis has been done by assuming the return maps to be piecewise linear. The proposed circuits are built with commerciallyavailable IC's. And their return maps and bifurcation trees are measured in the experiment. The design formulas are obtained for the bifurcation trees and they are confirmed by the simulation results. The proposed circuits are integrable by a standard BiCMOS technology.

Signal Transition Graphs (STG'S) [1] are Petrinets [2], which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfollding, has been proposed [3], [4]. OCN's can represent both causality and concurrency between two nodes by net stryctyre. In this paper, we propose an efficient algorithm to derive a logic function by generating sub-state space of a given STG using the structural properties of OCN. The proposed algorithm can be seem as a parallel algorithm for deriving a logic function.

A filter configuration that allows configuration of any transfer function used the state variable is discribed as an application of the second generation current conveyors (CCIIs) to RC networks. The filter types discussed are low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), all-pass filter (APF), and band-elimination filter (BEF). The filter circuit consists of four CCIIs and allows tandem connections. The device sensitivity and CCII's sensitivity to transfer coefficient are relatively low. The filter circuit that allow simultaneous configuration wewe fabricated. An experimental result at around 10kHz was obtained for the filters. In the case, the LPF, HPF, BPF, APF, and BEF characteristics are obtained at Q value of 5.0.

A new adaptive AR spectral estimation method is proposed. While conventional least-squares methods use a single windowing function to analyze the linear prediction error, the proposed method uses a different window for each frequency band of the linear prediction error to define a cost function to be meinemized. With this approach, since time and frequency resolutions can be traded off throughout the frequency spectrum, an improvement on the precision of the estimates is achieved. In this paper, a wavelet-like time-frequency resolution grid is used so that low-frequency components of the linear prediction error are analyzed through long windows and high-frequency components are analyzed through short ones. To solve the optimization problem for the new cost function, special properties of the correlation matrix are used to derive an RLS algorithm on the order of M2, where M is the number of parameters of the AR model. Computer simulations comparing the performance of conventional RLS and the proposed methods are shown. In particular, it can be observed that the wavelet-based spectral estimation method gives fine frequency resolution at low frequencies and sharp time resolution at high frequencies, while with conventional methods it is possible to obtain only one of these characteristics.

This paper is described on the realization of simulated inductance cercuit with parallel negative conductance and its application for an oscillator. The design's condition for realizing the circuit needs stability, narrow expance of elements, larger dynamic-range and lower sensitivity. A new floating simulated inductance circuit with parallel nagative conductance with two operational amplifiers, four resistors, and four capacitors is created by using the design's algorithm. And the elements sensitivity of the simulated circuit is superior to that of the conventional circuits. By experimenting with a resonance circuit, the author tested the sinusoidal oscillator's circuit of a parallel -GLC as an application in order to confirm the operation of the simulated inductance circuit with parallel negative conductance.

A miniature transceiver, including highly integrated MMIC front-end, for 1.9 GHz band personal handy phone system(PHS) has been developed. The terminal, adopting direct conversion transmitter and receiver technology, consists of four high-density RF circuit modules and a digital signal processing LSI with 2.7 V power supply. The four functional modules are a power amplifier, a transmitter,a receiver, and a frequency synthesizer. Each functional module includes one IC chip and passive LCR components connected with solder bumps on module substrate. The experimental miniature PHS handset has been fabricated to verify the design concepts of the miniature transceiver. The total volume of the developed PHS terminal is 60cc, including the 12cc front-end which comprises the four RF functional circuit modules. The air interface connection with the PHS base station simulator has been confirmed.

This paper examines the feasibility of a high frequency (moro than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed corrent-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 µm device paramenters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.

This study is aimed to derive a new theoretical solution for blind equalizers. Undr the common assumptions for this framework, it is found that the condition for blind equalization is directly associated with an eigenproblem, i.e. the tap coefficients of the equalizer appear as an eigenvector of a higher order statistics matrix. Computer simulations show that very fast convergence can be achieved based on the approach.

An improved gate current model of GaAs FET's is presented. A conventional gate current and the reverse breakdown characteristics. Conseguentli, the model has been determined only by the forward current model fails to fit measured results in the reverse bias range, under which power amplifiers operate. The proposed model improves this problem and shows a great enhancement in accuracy throughout the whole operation range of FET's. The model consists of three diodes and a resistor, which are standerd elements implemented in commercially available circuit simulators, and thus it can easily be used for analyzing performances of various FET circits.

We reveal fundamental electromagnetic characteristics of a basic proposition of the security tag system, being able to exclude a misjudgment caused by a neighboring reflective object, provided with a correlative detection, and that with a multi-resonant tag.

Table-form document structure analysis is an important problem in the document processing domain. This paper presents a new method called Box-Driven Reasoning (BDR) to robustly analyze the structure of table-form documents that include touching characters and broken lines. Real documents are copied repeatedly and overlaid with printed data, resulting in characters that touch cells and lines that are broken. Most previous methods employ a line-oriented approach, but touching characters and broken lines make the procedure fail at an early stage. BDR deals with regions directly in contrast with other previous methods and a reduced resolution image is introduced to supplement information deteriorated by noise. Experimental tests show that BDR reliably recognizes cells and strings in document images with touching characters and broken lines.