This paper reports on a high-speed silicon bipolar transistor with an fT and fMAX of over 40 GHz, we call it the Advanced Boro-silicated-glass Self-Aligned (A-BSA) transistor. In basic BSA technology, a CVD-BSG film is used not only as a diffusion source to form the intrinsic base and the link base regions but also as a sidewall spacer between the emitter and the base polysilicon electrodes. An A-BSA transistor offers three advancements to this technology: (1) a graded collector profile underneath the intrinsic base region to suppress the Kirk effect; (2) an optimized design of the link base region to prevent the frade-off effect between fT and base resistance; and (3) a newly developed buried emitter electrode structure, consisting of an N++-polysilicon layer, a platinum silicide layer, and a CVD tungsten plug, to prevent the emitter plug effect. Furthermore, our transistor uses a BPSG filled trench isolation to reduce parasitic capacitance and improve circuit performance. In this paper, we describe device design, process technology and characterization of the A-BSA transistor, with it we have performed several application ICs, operating at 10Gb/s and above. The A-BSA transistor achieved an fT of 41 GHz and an fMAX of 44 GHz under optimized conditions.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.

Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

A current controlled CMOS output driver was designed by using a temperature-insensitive reference current generator. It eliminates the need for overdesign of the driver transistor size to meet the delay specification at high temperature. Comparison with the conventional CMOS output driver with the same transistor size showed that the ground bounce noise was reduced by 2.5 times and the delay time was increased by 1.4 times, at 25 for 50pF load. The temperature variations of the DC pull-up and pull-down currents of the new output driver were 4% within the temperature range from -15 to 125 compared to the variations of 40 and 60% for pull-up and pull-down respectively for the conventional output driver. The temperature insensitivity of the reference current generator was achieved by multiplying two current components. one which is proportional to mobility and the other which is inversely proportional to mobility, by using a CMOS square root circuit. The temperature variation of the DC output current of the reference current generator alone was 0.77% within the entire temperature range from -15 to 125.

This paper deals with the synthesis of Petri nets. Partial languages adequately represent the concurrent behaviors of Petri nets. We first propose a construction problem for Petri nets, in which the objective is to synthesize a Petri net to exhibit the desired behavior specified as a partial language. We next discuss the solvability of this problem and last present the cutline of a solution technique.

The inclusion of the non-quasi-static effect is crucial in the simulation of the microwave circuits for MOS transistors. This report proposes a simple model which includes this effect in small-signal simulation. The simulated results are consistent with the measured data up to a frequency that is 30 times higher frequency than the cut-off frequency.

A 3V-50 MHz analog CMOS current-mode continuous-time active filter with a negative resistance load (NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. The inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5 µm CMOS n-well process. Simulation result shows the cutoff frequency of 50 MHz and power consumption of 2.4mW/pole with a 3V power supply.

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

A complex fuzzy adaptive decision feedback equalizer based on the RLS algorithm is proposed. The proposed equalizer not only improves the performance but also reduces the computational complexity compared with the conventional complex fuzzy adaptive equalizers under the assumption of perfect knowledge of the linear and nonlinear channels.

In order to highlight a rapid progress attained in the field of millimeter waves in Japan, this paper describes several key topics including transistors, integrated circuits, planar antennas, millimeter wave photonics, and others.

A circularly polarized omnidirectional antenna consisting of a vertical sleeve dipole and three pairs of titled parasitic elements set around it is proposed. The antenna is useful to mobile communication because the use of circular polarization allows us to suppress the effect of multi-path reflection waves (inverse rotation) caused by building walls and surface of the ground. The antenna with an omnidirectional pattern has a simple structure without a feeding network for radiating circular polarization. To understand the radiation characteristics of the proposed antenna, an approximation theory using the induced electromotive force method is introduced. As an example, using a fixed spacing of a quarter wave-length between the vertical dipole and the parasitic elements, the possibility of generation of circular polarization is examined. Then the computational results of the axial ratio and the input impedance are compared with the results of the numerical analysis using the moment method and the experimental result. The radiation characteristics of the antenna can be understood by using the approximation theory introduced here. As a summary of the study, the contour map of the axial ratio of circular polarization is depicted using the moment method. For practical design of this antenna, a small correction factor should be multiplied to the calculated results. From the experimental results, the proposed antenna has a gain of 2 dBi and 3 dB band-width with an axial ratio of about 8%.

This paper concerns a Petri-net-based model for describing reactive and concurrent systems. Although many high-level Petri nets have been proposed, they are insufficiently practical to describe reactive and concurrent systems in the detail modeling, design and implementation phases. They are mainly intended to describe concurrent systems in the rough modeling phase and lack in several important features (e.g., concurrent tasks, task communication/synchronization, I/O interface, task scheduling) which the most actual implementations of reactive and concurrent systems have. Therefore it is impossible to simulate and analyze the systems accurately without explicitly modeling these features. On the other hand, programming languages based on Petri nets are deeply dependent on their execution environments and not sophisticated as modeling and specification languages. This paper proposes MENDEL net which is a high-level Petri net extended by incorporating concurrent tasks, task communication/synchronization, I/O interface, and task scheduling in a sophisticated manner. MENDEL nets are a wide-spectrum modeling language, that is, they are suitable for not only modeling but also designing and implementing reactive and concurrent systems.

This paper describes a circuit analysis technique that includes all circuit elements used in transistor Colpitts quartz crystal oscillators. This technique is applied to a quartz crystal oscillator that has a tank circuit for selecting the oscillation frequency. The results obtained with this technique are compared with SPICE simulation results. Good agreement in the results clearly shows the validity of our technique.

We present a topological framework of stepwise specification for concurrent systems in this paper. Some of description techniques can make topologies on the system space. Such topologies corresponds to abstract levels of those description techniques. Using a family of such description techniques, one can specify systems stepwisely. This framework allows to bridge various DTs and modularizing, so that global properties and module properties of systems become to be related to each other. Within this framework, we show derivation of a LOTOS cpecification from temporal logic formulae. An extended version of LOTOS with respect to concurrency is used in this paper. A semantics including concurrency is introduced to do this in this method. The method presented in this paper is applied to mobile telecommunication.

Petri nets are widely recognized as a powerful model for discrete event systems. Petri nets have both graphical and mathematical features. Graphical feature provides an environment to design and to comprehend discrete event systems. Mathematical feature provides an analysis power for verifying several properties of such systems. Several analysis techniques have been proposed so far, such as a reachability (coverability) graph method, a matrix equation approach, reduction or decomposition techniques, a symbolic model method and an unfolding method. The unfolding method was introduced to avoid generating the reachability graph. Unfoldings are often used in the verification of asynchronous circuits. This paper focuses on an analysis of finite state systems, i.e., bounded nets, and discuss a reachability problem and a upper bound problem. Relations between these problems and an unfolding have been clarified to provide a novel method to resolve these problems.

The multichannel distortions of direct modulated laser diode were studied from the view point of rate equations. A novel technique for compensating the composite second order distortion (CSO) was proposed. Meanwhile, the related calibration procedures were indicated. After the compensation, 10 dB improvement in CSO was obtained

The author once defined the Ω-matrix and showed that it played an important role for estimating the number of solutions of a resistive circuit containing active elements such as CCCS's. The Ω-matlix is a generalization of the wellknown P-matrix. This paper gives the necessary and sufficient conditions for the Ω-matrix.

A high-frequency approximate method for calculating the diffraction by a smooth convex surface is presented. The advantage of this method is the validity of it in the caustic region of the creeping rays where the Geometrical Theory of Diffraction (GTD) becomes invalid. The concept used in this method is based on the Method of Equivalent Edge Currents (EEC), and the equivalent line currents for creeping rays which are derived from the diffraction coefficients of the GTD are used. By evaluating the radiation integral of these equivalent line currents, the creeping ray contribution which is valid within the caustic region is obtained. In order to check the accuracy and the validity of the method, the diffraction problem by a perfectly conducting sphere of radius a is solved by applying the method, and the obtained results are compared with the exact and the GTD solutions. It is confirmed from the comparison that the failure of the GTD near the caustic is removed in this method and accurate solution is obtained in this area for high-frequency (ka8). Furthermore, it is also found that this method is valid in the backward region (0θ90, θ is an observation angle mesuered from an incident direction), whereas not in the forward region (90θ180).

In this paper, Chay's bursting pancreatic β-cell model is updated to include a role for [Ca2+]ER, the luminal calcium concentration in the endoplasmic reticulum (ER). The model contains a calcium current which is activated by voltage and inactivated by [Ca2+]i. It also contains a cationic nonselective current (INS) that is activated by depletion of luminal Ca2+ in the ER. In this model, [Ca2+]ER oscillates slowly, and this slow dynamic drives electrical bursting and the [Ca2+]i oscillations. This model is capable of providing answers to some puzzling phenomena,which the previous models could not (e. g., why do single pancreatic β-cells burst with a low frequency while the cells in an islet burst with a much higher frequency ?). Verification of the model prediction that [Ca2+]ER is a primary oscillator that drives electrical bursting and [Ca2+]i oscillations in pancreatic β-cells awaits experimental testing. Experiments using fluorescent dyes such as mag-fura-2-AM could provide relevant information.