This paper presents a method of multiple fault diagnosis in sequential circuits by input-sequence pairs having sensitizing input pairs. We, first, introduce an input-sequence pair having sensitizing input pairs to diagnose multiple faults in a sequential circuit represented by a combinational array model. We call such input-sequence pair the sensitizing sequence pair in this paper. Next, we describe a diagnostic method for multiple faults in sequential circuits by the sensitizing sequence pair. From a relation between a sensitizing path generated by a sensitizing sequence pair and a subcircuit, the proposed method deduces the suspected faults for the subcircuits, one by one, based on the responses observed at primary outputs without probing any internal line. Experimental results show that our diagnostic method identifies fault locations within small numbers of suspected faults.

In this paper, we show that a parity function with n variables can be computed by a threshold circuit of depth O((log n)/c) and size O((2clog n)/c), for all 1c [log(n+1)]-1. From this construction, we obtain an O(log n/log log n) upper bound for the depth of polylogarithmic size threshold circuits for parity functions. By using the result of Impagliazzo, Paturi and Saks[5], we also show an Ω (log n/log log n) lower bound for the depth of the threshold circuits. This is an answer to the open question posed in [11].

An insertion loss, branching deviation and polarization dependent loss (PDL) as to a 2 N optical splitter using silica-based planar lightwave circuits has been investigated. New key technologies such as (1) a novel wedge type Y-branch, (2) an offset waveguide at the junction between the curved input waveguide and the Y-branch, and (3) low birefringence waveguides due to the appropriate dopant concentration of a cladding, have been devised and incorporated into the splitter. As a result, 2 N optical splitters with low average insertion loss ( 13.2 dB), low branching deviation ( 0.4 dB) and low PDL ( 0.2 dB) have been successfully developed.

We propose an InGaAlAs waveguide p-i-n photodiode (WG-PD) with a thick symmetric double-core for surface-hybrid integration onto optical platforms, which can be applied to low cost optical modules for access networks. The waveguide structure is designed to efficiently couple to flat-ended single mode fibers while maintaining low-voltage (less than 2 V) operation. Crystal growth conditions and a passivation technique are also investigated for obtaining high responsivity, low dark current and highly reliable operation. Fiber-coupled responsivity as high as 0.95 A/W, at a 1.3-µm wavelength, and vertical coupling tolerance as wide as 2.6 µm are demonstrated for a dispersion-shifted fiber (DSF) coupling at an operating voltage of 2 V. Dark current is as low as 300 pA at 25 and 12 nA at 100. A temperature accelerated aging test is performed to show the feasibility of using the WG-PD in long-term practical applications.

With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.

Micromachined sensors and actuators applied with electrostatic fields are getting widely developed. At the same time, "electrets," which are dielectrics carrying non-equilibrium permanent space charges or polarization distribution, are in demand because they improve the transducer characteristics. In this paper, we have reported on our successful fabrication of silicon dioxide electrets with extremely superior long-term charge stability by plasma chemical vapor deposition (PCVD). We have also reported on the correlation between the deposition conditions, the long-term charge stability and thermally stimulated current (TSC). Finally, the characterization of the long-term stable electrets will be described and discussed.

Weakness of a block cipher, which has provable immunity against linear cryptanalysis, is investigated. To this end, the round transformation used in MISTY, which is a data encryption algorithm recently proposed by M. Matsui from Mitsubishi Electric Corporation, is compared to the round transformation of DES from the point of view of pseudrandom generation. An important property of the MISTY cipher is that, in terms of theoretically provable resistance against linear and differential cryptanalysis, which are the most powerful cryptanalytic attacks known to date, it is more robust than the Data Encryption Standard or DES. This property can be attributed to the application of a new round transform in the MISTY cipher, which is obtained by changing the location of the basic round-function in a transform used in DES. Cryptograohic roles of the transform used in the MISTY cipher are the main focus of this paper. Our research reveals that when used for constructiong pseudorandom permutations, the transform employed by the MISTY cipher is inferior to the transform in DES, though the former is superior to the latter in terms of strength against linear and differential attacks. More specifically, we show that a 3-round (4-round, respectively) concatenation of transforms used in the MISTY cipher is not a pseudorandom (super pseudorandom, respectively) permutation.

When N oscillators are coupled by one resistor, we can see N-phase oscillation, because the system tends to minimize the current through the coupling resistor. Moreover, when the hard oscillators are coupled, we can see N, N - 1, , 3, 2-phase oscillation and get much more phase states. In this study, the two types of coupled oscillators networks with third and fifth-power nonlinear characteristics are proposed. One network has two-dimensional hexagonal structure and the other has two-dimensional lattice structure. In the hexagonal circuit, adjacent three oscillators are coupled by one coupling resistor. On the other hand, in the lattice circuit, four oscillators are coupled by one coupling resistor. In this paper we confirm the phenomena seen in the proposed networks by circuit experiments and numerical calculations. In the system with third-power nonlinear characteristics, we can see the phase patterns based on 3-phase oscillation in the hexagonal circuit, and based on anti-phase oscillation in lattice circuit. In the system with fifth-power nonlinear characteristics, we can see the phase patterns based on 3-phase and anti-phase oscillation in both hexagonal and lattice circuits. In particular, in these networks, we can see not only the synchronization based on 3-phase and anti-phase oscillation but the synchronization which is not based on 3-phase and anti-phase oscillation.

In this paper, we propose a practical and secure electronic voting scheme which meets the requirements of large scale general elections. This scheme involves voters, the administrator or so called the government and some scrutineers. In our scheme, a voter only has to communicate with the administrator three times and it ensures independence among voters without the need of any global computation. This scheme uses the threshold cryptosystem to guarantee the fairness among the candidate's campaign and to provide mechanism for achieving the function that any voter can make an open objection to the tally if his vote has not been published. This scheme preserves the privacy of a voter against the administrator, scrutineers, and other voters. Completeness, robustness, and verifiability of the voting process are ensured and hence no one can produce a false tally, corrupt or disrupt the election.

Two high output-resistance CMOS current mirrors suitable for a low-voltage operation and achieving a high output-swing are presented. They incorporate a modified regulated-cascode, which employs a current-mode amplifier. The main architecture concepts and their detailed schematic examples are discussed. SPICE simulation comparison is shown and the properties of each architecture are pointed out.

As a low-cost optical transceiver for access network systems, we propose a new monolithic transceiver photonic integrated circuit (PIC) fabricated by bandgap energy controlled selective metalorganic vapor phase epitaxy (MOVPE). In the PIC, all optical components are monolithically integrated. Thus, the number of optical alignment points is significantly reduced and the assembly costs of the module is decreased compared to those of hybrid modules, that use silica waveguides. Moreover, by using selective MOVPE, extremely low-loss buried heterostructure waveguides can be fabricated without any etching. In-plane bandgap energy control is also possible, allowing the formation of active and passive core layers simultaneously without complicated fabrication. The transceiver PIC showed fiber-coupled output power of more than 1 mW and receiver bandwidth of 7 GHz. Modulation and detection operations at 500 Mb/s were also demonstrated. As a cost effective fabrication technique for monolithic PICs, bandgap energy controlled selective MOVPE is a promising candidate.

A low dark current CCD linear image sensor with pixels consisting of a photodiode and a storage area has been developed. In order to suppress the dark current, the wafer process has been improved. An impurity profile of a photodiode was modified to minimize depletion width, which was monitored by the photodiode potential. Surface states under the storage gate were decreased by hydrogen annealing with plasma-deposited silicon nitride as an inter metal dielectric film. As the isolation dose decreased, the dark current both in the photodiode and in the storage region were effectively suppressed. Finally, low dark currents of 5 pA/cm2 at photodiode and 120 pA/cm2 at storage area were obtained.

Two methods of the second step of the elliptic curve method for factoring are known. One is the standard method that is similar to the second step of the p-1 method, and the other is the Brent method that is based on the "birthday paradox." In this paper, we propose a revised standard method and a revised Brent method. On an average, the revised standard method is the most efficient, the standard method is the second efficient, the revised Brent method is the third and the Brent method is the fourth. If the largest prime factor on the order of an elliptic curve is congruent to 1 modulo 3, then the revised Brent method becomes more efficient than the standard method. By applying these methods to unsolved problems in the Cunningham project, we found 18 new prime factors. The largest prime factor among them was 43-digits.

This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.

This paper describes the technological issues in achieving a low-cost hybrid WDM module for access network systems. The problems which should be resolved in developing a low-cost module are clarified from the viewpoint of the module assembly in mass production. A design concept for a low-cost module suitable for mass production is indicated, which simplifies the alignment between a laser diode and a waveguide, and reduces the number of the components such as lenses and mirrors. The low-cost module is achieved by employing a flip-chip bonding method with passive alignment using a spot-size converter integrated laser diode (SS-LD) and p-i-n waveguide photodiodes (WGPDs) on a planar lightwave circuit (PLC) platform. We confirm that the SS-LD and the WGPD provide high coupling efficiency with a large tolerance for passive alignment. To achieve a high-sensitivity receiver, the module is designed to employ an asymmetric PLC Y-splitter that prefers a PD responsivity to an LD output power because of the high-coupling efficiency of the LD, and to employ a bare preamplifier mounting to reduce the parasitic capacitance into a preamplifier. We also demonstrate the dynamic performance for a 50-Mb/s burst signal, such as a high sensitivity, an instantaneous AGC response, and a small APC deviation of the transceiver.

In this paper, we apply the method of relating learning to hypothesis testing [6] to study average generalization performance of concept learning from noisy random training examples. A striking aspect of the method is that a learning problem with a so-called ill-disposed learning algorithm can equivalently be reduced to a simple one, and for this simple problem, even though a direct and exact calculation of the learning curves might still be impossible, a thorough empirical study can easily be performed. One of the main advantages of using the illdisposed algorithm is that it well models lower quality learning in real situations, and hence the result can provide useful implications as far as reliable generalization is concerned. We provide empirical formulas for the learning curves by simple functions of the noise rate and the sample size from a thorough empirical study, which smoothly incorporates the results from noise-free analysis and are quite accurate and adequate for practical applications when the noise rate is relatively small. The resulting learning curve bounds are directly related to the number of system weights and are not pessimistic in practice, and apply to learning settings not necessarily within the Bayesian framework.

This paper proposes a novel VLSI architecture capable of processing the Lempel-Ziv-based data compression algorithm very fast. The architecture is composed of five main blocks, i.e., a PE-based Match Block, a Consecutive Hit Checker, a Pointer Generator, a Length Generator, and a Code Packer. Flexibility of the PE-based structure makes it possible to adapt to various buffer sizes without any loss of speed or additional control overhead. Since it is designed as a VLSI-oriented architecture, it has simple control logic circuitry. It processes exactly one character per clock cycle and the update of a dictionary buffer is automatically done, therefore it does not require additional accumulated shift operations to prepare for the dictionary buffer. The shift operations have been major problems commonly found in most other architectures. When implemented with the currently available 0.5µm CMOS technology, it is proven by critical path analysis that the architecture can achieve over 100 mega samples (characters) per second with a clock frequency of 100 MHz. This is fast enough for real time data compression for many applications.

This paper describes the design and performance of optical components for in-service fiber testing and monitoring in optical subscriber loops. As the number of test fibers increases, compact and cost-effective components are becoming more important. To meet this need, we have developed a highly-dense hybrid structure for optical couplers and filters, which both play key roles in testing systems. It was realized by utilizing a polyimide-base thin film filter and a waveguide-type wavelength insensitive coupler. This component operates by combining a signal and a test light with a ratio of 80/20% and isolating the test light with a value of 50 dB. The experimental samples were successfully fabricated with an excess loss of 1 dB, a return loss of 40 dB, a plolarization dependent loss (PDL) of 0.3 dB, and good environmental and mechanical stability. We successfully applied the samples to an optical branch module (OBM), and achieved a component density twice that of a conventional module. The optical characteristics of the OBM met our target values. The results we obtained for termination cords incorporating the polyimide-base filter were also satisfactory.

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

The Time-Slicing paradigm is a newly developed method for the training of neural networks for speech recognition. The neural net is trained to spot the syllables in a continuous stream of speech. It generates a transcription of the utterance, be it a word, a phrase, etc. Combined with a simple error recovery method the desired units (words or phrases) can be retrieved. This paradigm uses a recurrent neural network trained in a modular fashion with natural connectionist glue. It processes the input signal sequentially regardless of the input's length and immediately extracts the syllables spotted in the speech stream. As an example, this character string is then compared to a set of possible words, picking out the five closest candidates. In this paper we describe the time-slicing paradigm and the training of the recurrent neural network together with details about the training samples. It also introduces the concept of natural connectionist glue and the recurrent neural network's architecture used for this purpose. Additionally we explain the errors found in the output and the process to reduce them and recover the correct words. The recognition rates of the network and the recovery rates for the words are also shown. The presented examples and recognition rates demonstrate the potential of the time-slicing method for continuous speech recognition.