This study is aimed to derive a new theoretical solution for blind equalizers. Undr the common assumptions for this framework, it is found that the condition for blind equalization is directly associated with an eigenproblem, i.e. the tap coefficients of the equalizer appear as an eigenvector of a higher order statistics matrix. Computer simulations show that very fast convergence can be achieved based on the approach.

Table-form document structure analysis is an important problem in the document processing domain. This paper presents a new method called Box-Driven Reasoning (BDR) to robustly analyze the structure of table-form documents that include touching characters and broken lines. Real documents are copied repeatedly and overlaid with printed data, resulting in characters that touch cells and lines that are broken. Most previous methods employ a line-oriented approach, but touching characters and broken lines make the procedure fail at an early stage. BDR deals with regions directly in contrast with other previous methods and a reduced resolution image is introduced to supplement information deteriorated by noise. Experimental tests show that BDR reliably recognizes cells and strings in document images with touching characters and broken lines.

We reveal fundamental electromagnetic characteristics of a basic proposition of the security tag system, being able to exclude a misjudgment caused by a neighboring reflective object, provided with a correlative detection, and that with a multi-resonant tag.

The recurrence method is useful for numerical calculation of the Bassel function Jv(x) of complex order v. The necessary total number of the recurrences in this method has been examined for the real order v, but it is known only for limited ranges of the real order v and the variable x, and it is not known for the complex order v. This letter proposes a new algorithm which increases the total number of the recurrences gradually, and which stops the calculation automatically when the approximate Bessel function with a necessary precision is obtained.

This letter describes the collector-short technique for improving the blocking capability of the lateral IGBT (LIGBT) on the SOI film. The concept of our proposed techniques is to prevent the injection of the minority carrier from the collector region to the high electric field area. This can be done by replacing the p+-collector layer at the sharp corner of the collector region, where the potential distribution in the device is subject to the diffusion curvature effect of the n-buffer layer, with the n+-collector-short layer. By only introducing the collector-short region to the sharp corner of the collector region, an increase of about 40 V in the breakdown voltage over the LIGBT without the collector-short region can be achieved.

The base transit time of an Aluminum-graded-base PNp AlGaAs/GaAs heterojunction bipolar transistor (HBT) was studied in order to clarify the effect of aluminum grading in the base. Theoretical analysis using a classical drift diffusion model with velocity saturation at the base-collector junction and a high base quasielectric field (58 keV/cm) created by 20%-aluminum linear grading in a 400 base, leads to a base transit time (τb) of 0.9 ps. The base transit time is reduced by four times, compared to the base transit time of 3.6 ps without aluminum grading in the base. In order to demonstrate this advantage, we fabricated aluminum-graded-base PNp AlGaAs/GaAs heterojunction transistor which employs a 20%-aluminum linear graded 400 -wide base. The device with a 2 µm 10 µm emitter showed high RF performance with a cut-off frequency (ft) of 37 GHz and a maximum oscillation frequency (fmax) of 30 GHz at a collector current density of 3.4 104 A/cm2. Further analysis using direct parameter extraction of a small signal circuit model under the collector current density of 1.1-9.9104 A/cm2 indicated the intrinsic transit time, which is the sum of the base transit time and the collector depletion layer transit time (τSC), was as low as 2.3 ps under lowinjection level. Subtracting the collector depletion-layer transit time from the intrinsic time leads to a base transit time of 1.1 ps, which is close to the theoretical base transit time and is the shortest value ever reported. The structure is very attractive for pnp-type AlGaAs HBTs combined with Npn HBTs for complementary applications.

This paper describes the design of a high-speed 4-2 compressor for fast multipliers. Through the survey of the six kinds of representative conventional 4-2 compressor (RBA 1-3 and NBA 1-3) in both the redundant binary (RB) and the normal binary (NB) scheme, we extracted two problems that degrades the operating speed. The first is the use of multi-input complex gates and the second is the existence of transmission gates (TG) at the input and/or output stages. To solve these problems, we propose high-speed 4-2 compressors using the RB scheme, which we call the high-speed redundant binary adders (HSRBAs). Six kinds of HSRBAs, HSRBA 1-6, were derived by making the Boolean equations suitable for high-speed CMOS circuits. Among them, HSRBA2, HSRBA4 and HSRBA6 have no multi-input complex gate and input/output TG, and perform at a delay time of 0.89 ns which is the fastest of all 4-2 compressors. We investigated the logical relation between HSRBAs and conventional 4-2 compressors by analyzing the Boolean equations for each circuit. This investigation shows that all the conventional redundant binary adders RBA1-3 have the same logic structures as HSRBA2. We also showed the conventional normal binary adders NBA1-3 have the same logic structures as HSRBA1, HSRBA3 and HSRBA5, respectively. This implies all 4-2 compressors can be derived from the same equation regardless of RB or NB. We applied the HSRBA2 to a 5454-bit multiplier using 0.5-µm CMOS technology. The multiplication time at the supply voltage of 3.3 V was 8.8 ns. This is the fastest 5454-bit multiplier with 0.5-µm CMOS so far, and 83% of the speed improvement is due to the high speed 4-2 compressor.

It is demonstrated with the Berlekamp-Massey shift-register synthesis algorithm that the linear complexity value of binary complementary sequences is at least 3/4 of the sequence length. For some sequence pairs the linear complexity value can be even 0.98 times the sequence length. In the light of these results strongly non-linear complementary sequences are considered suitable for information security applications employing the spread-spectrum (SS) technique.

Recently, a number of concurrency control algorithms have been proposed for multidatabase system (MDBS) concurrency control methods (CCMs) and the most challenging issue of them has been a concern about how to ensure global serializability (GSR). In this paper, we examine two concurrency control algorithms of MDBS through simulation approach: optimistic ticket method (OTM) and global ticket method (GTM). In historical note, OTM is known to be the first practical solution, since this approach ensures GSR by way of automatically resolving indirect conflicts among global transactions without making any restrictions on local CCMs. However, OTM is expected to yield poor performance since it enforces all global transactions to take a local ticket which causes direct conflicts between them. In GTM, the global transaction manager in an MDBS assigns a global ticket to global transactions rather than accessing a local ticket as in OTM. Our experimental results showed that GTM outperforms OTM in cases that short timeout values are given. However, in case that the timeout value relatively becomes long, our results demonstrated that OTM outperforms GTM.

This paper concerns multiple-valued logical function realized by asynchronous circuit that may have feed-back loops and its completeness problems. The first aim is to give mathematical definition of an asynchronous circuit over multiple-valued logical functions and of the realization of multiple-valued logical function by means of an asynchronous circuit. For asynchronous element, the definition of circuit construction and initialization are very sensitive. A slight modification may have a considerable influence on the completeness. We consider three types of completeness (LF-, GS-, NS-completeness) for a set of multiple-valued logical functions. The LF-completeness means completeness of logical functions realized loop-free cirucit. The GS-completeness means completeness under general initialization assumption. The NS-completeness measn completeness under initialization by input assumption. The second aim is to give a completeness criterion for each type of completeness. This aim is realized for LF-completeness in general case and GS-completeness in ternary case. A completeness criteria for GS-completeness and NS-completeness are given under strong conditions.

A decision circuit with a function of detecting the phase difference between input data and clock signal is presented. Direct coupled FET logic (DCFL) was used for basic gates. The circuit architecture was chosen to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. In GaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mVpp up to 10 Gb/s. Linear and wide-range phase detection was achieved as well as an ability to compensate the variation of transition density, input bias and temperature.

We define two restricted classes of Boolean circuits by assuming the following conditions on underlying graphs of circuits, and prove, for each class, nonlinear lower bounds on size of circuits computing cyclic shifts: for any two paths from the same input to the same output node, the sequences of depths of nodes along these paths are the same. A circuit is partitioned into subcircuits such that each subcircuit has at most o(log n) output gates and the multivalued circuit obtained from the partition is directed tree. These two conditions are driven from different points of view, and lower bounds are established for each one of them.

This paper discusses the design of a small sensing device for EMI measurement which has equivalent characteristics to the absorbing clamp method, and reports the results on evaluation of the device. The device can be applied to the inspection apparatus for products such as power tools to examine conformance to EMI regulations of electromagnetic radiation spectrum. For reducing the scale of the EMI inspection apparatus, new matching circuit being replaced with the absorbing clamp method is adopted in the sensing device. Length of the sensing device is smaller than one twelfth of a wavelength of the measuring frequency in order to regard the sensing device as a concentrated constant circuit. The matching circuit is a resonant circuit which consists of a coaxial coupled transformer and a variable capacitor, and the transformer is a spiral copper tube in which a pair of AC power line wires passes. Resonant frequency of the circuit is tuned to the measuring frequency by adjusting the variable capacitor so that the circuit would terminate the power line by impedance zero. Thus interference current propagating along the power line from a product is absorbed, and observed by means of a VHF current probe which is settled in the matching circuit. A simple circuit for measurement of noise amplitude distribution (NAD) of interference current was developed as well as an equation to estimate quasi-peak value from the NAD. Result of measurement by the sensing device and proposed procedure confirmed good correlation with the standard absorbing clamp method, and deviation was within 3dB. Measurement time was reduced to 25 s per product, and the in-line EMI checker with new sensing device can be employed in a mass production line.

We have developed the Epi-Base SATURN process as a silicon bipolar process technology which can be applied to optical transmission LSIs. This process technology, to which low temperature selective epitaxial growth technology is applied, is based on the SATURN process. By performing selective epitaxial growth for base formation in 2 steps, transistors with a 40GHz maximum cut-off frequency have been fabricated. In circuit simulation based on SPICE parameters of transistors, the target performance required for 2.4 Gbit/s optical interface LSIs has been achieved.

We have developed inlaid copper interconnects employing amorphous Ti-Si-N barrier metal. The interconnect resistivity is 1.90.1 µΩcm. Ti-Si-N films were shown to be amorphous by X-ray diffraction measurements. The amorphous structure was thermal stable, even after annealing at 600 for 30 minutes in an Ar ambient. The atomic composition of the film was identified as Ti : Si : N=1 : 0.6 : 1.6. The films were found to be under tensile stress of 0.3 Gpa. The resistivity is about 0.5 mΩcm at room temperature. The diffusion barrier characteristics were evaluated by n+/p and p+/n junction leakage measurements. No degradation of leakage characteristics was observed for these diodes, even after annealing at 600 for 30 minutes in an N2/H2 ambient. The amorphous Ti-Si-N barrier metal is a promising candidate for application in deep-submicron high-speed ULSIs.

A cumulant-based lattice algorithm for multichannel adaptive filtering is proposed in this paper. Proposed algorithm takes into account the advantages of higer-order statistics, that is, improvement of estimation accuracy, blindness to colored Gaussian noise and the possibility to estimate the nonminimum-phase system etc. Without invoking the Instrumental Variable () method as used in other papers [1], [2], the algorithm is derived directly from the recursive pseudo-inverse matrix. The behavior of the algorithm is illustrated by numerical examples.

Circuit simulators are used to verify circuit functionality and to obtain detailed timing information before the expensive fabrication process takes place. They have become an essential CAD tool in an era of sub-micron technology. We have developed a new event-driven MOS circuit simulator to replace a direct method circuit simulator. In our simulator, partitioned subcircuits are analyzed by a direct method matrix solver, and these are controlled by an event-driven scheme to maintain accuracy. The key of this approach is how to manage events for circuit simulation. We introduced two types of events: self-control events for a subcircuit and prediction correcting events between subcircuits. They control simulation accuracy, and bring simulation efficiency through multi-rate behavior of a large scale circuit. The event-driven scheme also brings some useful functions which are not available from a direct method circuit simulator, such as a selected block simulation function and a batch simulation function for load variation. We simulated logic modules (buffer, adder, and counter) with about 1000 MOSFETs with our event-driven MOS circuit simulator. Our simulator was 5-7 times faster than a SPICE-like circuit simulator, while maintaining the less than 1% error accuracy. The selected block simulation function enables to shorten simulation time without losing any accuracy by selecting valid blocks in a circuit to simulate specified node waveforms. Using this function, the logic modules were simulated 13-28 times faster than the SPICE-like circuit simulator while maintaining the same accuracy.

In order to reduce the ever increasing cost for ULSI manufacturing due to the complexity of integrated circuits, dramatic simplification in the logic LSI architecture as well as the very flexible circuit configuration have been achieved using a highfunctionality device neuron-MOSFET (γMOS).In γMOS logic circuits, however, computations based on the multiple-valued logic is the key for enhancing the functionality. Therefore, much higher accuracy of processing is required. After brief description of the operational principle of γMOS logic, the relationship between the number of multiple logic levels and the functionality enhancement is discussed for further enhancing the functionality of γMOS logic circuits by increasing the number of multiple logic levels, and the accuracy requirements for the manufacturing processes are studied. The order of a few percent accuracy is required for all principal device structural parameters when it is aimed to handle 50-level multiple-valued variable in the γMOS logic circuit.

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.

The power distribance appeared at a typical electric power system, which can be modeled by a simplified distributed circuit, is discussed. The electric power and the point where its power is injected are then estimated to suppress the power distrbance.