The concentration of the electric field at the edge of the electrode has been simulated in several types of flat DRAM cell capacitors with high permittivity dielectrics. The results indicated that the permittivity of the material surrounding the edge of the electrode as well as the geometrical structure affected the concentration of the electric field. The electric field strength was minimized and most evenly distributed by utilizing the structure in which the sidewall of the capacitor dielectric was terminated at the edge of the electrode by a low-dielectric constant insulator. High-precision fabrication of the capacitor's profile is required for the minimization and uniformity of the electric field.

A method for the recognition of Arabic printed scripts entered from an image scanner is presented. The method uses the Hough transformation (HT) to extract features, Dynamic programming (DP) matching technique, and a topological classifier to recognize the characters. A process of characters recognition is further divided into four parts: preprocessing, segmentation of a word into characters, features extraction, and characters identification. The preprocessing consists of the following steps: smoothing to remove noise, baseline drift correction by using HT, and lines separation by making an horizontal projection profile. After preprocessing, Arabic printed words are segmented into characters by analysing the vertical and the horizontal projection profiles using a threshold. The character or stroke obtained from the segmentation process is normalized in size, then thinned to provide it skeleton from which features are extracted. As in the procedure of straight lines detection, a threshold is applied to every cell and those cells whose count is greater than the threshold are selected. The coordinates (R, θ) of the selected cells are the extracted features. Next, characters are classified in two steps: In the first one, the character main body is classified using DP matching technique, and features selected in the HT space. In the second one, simple topological features extracted from the geometry of the stress marks are used by the topological classifier to completely recognize the characters. The topological features used to classify each type of the stress mark are the width, the height, and the number of black pixels of the stress marks. Knowing both the main group of the character body and the type of the stress mark (if any), the character is completely identified.

In this paper, the effects of the grouping and the addressing methods on the accuracy and the response time in a visual search task were investigated. Four grouping conditions (4, 8, 16 and 32 groups) and four addressing methods (random, ordered, cartesian and polar) were selected in the experiment. For each combination of grouping and addressing methods, subjects repeated the search task 30 times. No remarkable differences of the percent correct were observed both among the levels of grouping and among the addressing methods. The mean response time increased with the increase of the number of groups. Moreover, the interaction between addressing methods and grouping for both percent correct and response time was clarified.

Breakdown fields and the charges to breakdown (QBD) of oxides increased after UV/Cl2 pre-oxidation cleaning. This is due to decreased residual metal contaminants on silicon surfaces in the bottom of the LOCOS region after wet cleaning. Treatment in NH4OH, H2O2 and H2O prior to UV/Cl2 cleaning suppressed increases in surface roughness and kept leakage currents through the oxides after UV/Cl2 cleaning as low as those after wet cleaning alone. The large junction leakage currents--caused by metal contaminants introduced during dry etching--decreased after UV/Cl2 cleaning which removes the contaminated layer.

We define the communication complexity of a perfect zero-knowledge interactive proof (ZKIP) as the expected number of bits communicated to achieve the given error probabilities (of both the completeness and the soundness). While the round complexity of ZKIPs has been studied greatly, no progress has been made for the communication complexity of those. This paper shows a perfect ZKIP whose communication complexity is 11/12 of that of the standard perfect ZKIP for a specific class of Quadratic Residuosity.

New illumination principle for photolithography is investigated. As the optical microlithography approaches its own limit, it becomes apparent that the simple extrapolation of the present technology is not sufficient for the future demands. This paper introduces the new imaging technology that overcomes such a boundary. First, the basic imaging formulae are analyzed and the illumination light is classified into 4 cases. 3-beam case and 2-beam case carry the object information, and the comparison of these 2 cases is carried out theoretically. It can be shown that the 2-beam case has greater depth of focus than that of the 3-beam case, though it has inferior contrast at the best focus. Since this degradation, however, has little effect, the enlargement of the depth of focus can be achieved. In reality, 2-dimensional imaging must be considered. Quadrupole effect can be deduced by the results of the analysis. It shows great improvement in the depth of focus near resolution limit. As it can be applied to the conventional masks, it can be a promising candidate for fhe future lithography. Experimental results are also shown to demonstrate the analysis.

This letter describes an MOS operational transconductance amplifier and an MOS four-quadrant analog multiplier using the quadritail cell, which provides an output current proportional to the square of a differential input voltage. As a result, a linear transconductance amplifier and a quarter-squarer multiplier can be obtained in theoretical circuit analysis.

This paper describes the endurance of a ceramic hydrophone to measure high acoustic pressures at the focal point of Extracorporeal Shockwave Lithotripter (ESWL).

This paper describes a novel Recessed Stacked Capacitor (RSTC) structure for 256 Mbit DRAMs, which can realize the requirements for both fine-pattern delineation with limited depth of focus and high cell capacitance. New technologies involved are the RSTC process, 0.25 µm phase-shift lithography and CVD-tungsten plate technology. An experimental memory array has been fabricated with the above technologies and 25 fF/cell capacitance is obtained for the first time in a 0.61.2 µm2 (0.72 µm2) cell.

The newly developed GaAs-pin/SLM, that is structured with a GaAs-pin diode photodetector and a ferroelectric liquid crystal as the light phase modulator, shows the accumulative thresholding characteristic against the optical energy of the write-in pulse train. We experimentally investigate this characteristic and discuss its applications to optical parallel processings.

To improve the stability and the power supply rejection ratio (PSRR) of the voltage limiter circuit used in high-density DRAM's we present a voltage limiter circuit with pole-zero compensation. Analytical expressions that describe the stability of the circuit are provided for comprehensive consideration of circuit design. Voltage limiters with pole-zero compensation are shown to have excellent performance with respect to the stability, PSRR, and circuit area occupation. The parasitic resistances in internal voltage supply lines, signal transmission lines, and transistors are important parameters determining the stability of pole-zero compensation. Evaluation of a 16-Mbit test device revealed internal voltage fluctuations of 6% during operation of a chip-internal circuit, a phase margin of 53, and a PSRR of 30 dB.

A multi-valued addressing scheme is proposed for a high speed, high packing density memory system. This scheme is a level-multiplex addressing scheme instead of standard time-multiplex addressing scheme, and provides all address signals to the DRAM at the same time without increasing the address pin counts. This scheme makes memory matrix strechable and achieves the low power dissipation using the enhanced partial array activation. The 16 Mb stretchable memory matrix DRAM (16MbSTDRAM) is examined using this addressing design. A power dissipation of 121.5 mW, access time of 30 ns, and 20 pin have been estimated for 3.3 v 16MbSTDRAM with X/Y=15/9 adress configuration. The low power battery-drive memory system for such as the note-book or the handheld-type personal computers can be realized by the STDRAMs with the multi-valued addressing scheme.

If a perspective of the "256M/1G era" were to be made from this present, namely the last stage of the development of 64 M DRAMs, the process technologies will show a variety of progress. Some of them would remain only in the extension of the present ones, but others would show a fundamental change including their technological constitutions. The optical lithography will survive even the "256M/1G era" mainly with the innovations of mask technologies. The etching technologies will remain basically the same as the present ones, but will be much more refined. The studies on plasma/redical related surface reactions, however, will bring a variety of surface treatment technologies of new function. The interconnection technologies will encounter various kinds of difficulties both in materials and in processign, and mechanical processing will become one of ULSI processing technologies. The shallow junction technology will merge with the metallization and epitaxial growth technology. The thin dielectrics will approach a critical situation, and it might enhance the device structural change to three dimensional ones. Corresponding to this, the necessity of "vertical processing" will become larger. The bonding SOI technology might overcome these situations of increasing difficulties. On the other hand, the contamination control will be the base of these technology innovations and improvements, exploring a new technology field in addition to the conventional process technology fields.

We have successfully developed an optical receiver and a laser driver circuit which were implemented with 0.35 µm GaAs JFETs (junction Field Effect Transistors). The 0.35 µm GaAs. JFET had the typical transconductance of 480 mS/mm with small drain conductance. An interdigit MSM (Metal Semiconductor Metal) -type photodetector and the JFETs were monolithically integrated on a GaAs substrate for the optical receiver. The fabricated optical receiver demonstrated Gb/s operation with a very low power consumption of 8.2 mW. The laser driver circuit operated at up to 4.0 Gb/s.

GaAs MESFETs with a p-buffer layer (or a buried p-layer) are important devices for high-speed GaAs ICs. To study what conditions are required as a good substrate for ICs, we have investigated, by two-dimensional simulation, small-signal parameters and drain-current transients of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate. It is shown that the introduction of a p-buffer layer is effective to improve the transconductance and the cuttoff frequeycy. These parameters are not degrade even if the p-layer doping is increased and a neurtral p-region exists. It is also shown that drain-current drifts and hysteresis in I-V curves can occur in a case with a p-buffer layer, too. It is concluded that the introduction of a relatively highly-doped p-layer on a substrate with low acceptor and electron trap (EL2) densities is effective to realize the stable and high performance of GaAs MESFETs.

A new algorithm for timing driven placement based on the fuzzy theory is proposed. In this method, the signal delay on the longest path, the chip area and the total wire length can be simultaneously minimized. Introducing the probability measures of fuzzy events, falling down into the local optimal solutions can be avoided. At first, we define the fuzzy placement relation using the graph distance matrix and fuzzy distance relation matrix, and we give a new placement method based on the fuzzy placement relation and the probability measures of fuzzy events. Secondly, we extend this placement method so as to apply to the timing driven placement problem by introducing a fuzzy membership functions which represent the signal delay on the longest path and the chip area. Finally, experimental results are shown to compare our method with one of the previous methods.

An effective bitline technique for high density DRAMs is studies. The open-type bitline structure where the bitlines are activated alternately can decrease the bitline noises and the current dissipation in memory cell arrays. In spite of several disadvantages inherent to the open-type bitline structure, this technique is found to get the larger read-out signal than the conventional bitline configurations for the DRAMs of 64 Mb and beyond. The effectiveness is confirmed with the measurement of the test-chips. This technique is expected to be more efficient for DRAMs of higher density, where the contribution of the inter-bitline capacitance is increased.

A Pt-based gate and photochemical dry etching were developed to fabricate N-InAlAs/InGaAs HEMT ICs. The N-InAlAs/Pt contact showed a Schottky barrier at 0.82 eV, about 0.3 eV larger than ΔEc, and nearly ideal I-V characteristics. Its main disadvantage was the excess penetration of Pt into InAlAs. We proposed a thin-Pt/Ti/Au multilayer gate, more thermally stable than the thick-Pt gate, where Ti layer suppresses the above problem with Pt. The multilayer gate also showed a Schottky barrier (φ) of 0.83 eV and an edeality dactor of 1.1. The high φ value makes it possible to fabricate an E-mode N-InAlAs/InGaAs HEMT. We also developed photochemical selective dry etching using CH3Br gas and a low-pressure mercury lamp. The etching selectivity was 25 at an etch rate of 17 nm/min for InGaAs and 0.7 nm/min for InAlAs. The 1.2-µm-gate E-mode HEMT fabricated using the Pt-based gate and photochemical etching had an excellent peak transconductance of 620 mS/mm with a threshold voltage of +0.03 V. The standard deviation of the threshold voltage of E-mode HEMTs on a 2-inch wafer was 20 mV at an average of +0.088 V. These results indicate the effectiveness of the Pt-based gate and photochemical etching for fabricating N-InAlAs/InGaAs HEMT ICs.

This paper describes a new method for designing switching software called DDL (Data Driven Logic). The new design method adopts the dataflow concept and graphical programming using a dataflow diagram. A dataflow diagram is used for software representation, and a dataflow mechanism is emulated on a conventional von Neumann processor. The DDL method has the following advantages; (1) general advantages of dataflow software; i.e. easily understandable programs using graphical representations, and easy description of parallelism, (2) modular design using reusable software components, (3) easy design and programming with a graphical user interface. This paper presents the general concepts and structure of DDL. It also discusses the dataflow emulation mechanism, the DDL software development process, the DDL programming environment, an evaluation of the DDL call processing program applied to a commercial PABX, and some unsolved problems of DDL.

In this letter, a generalized syndrome polynomial is proposed from which several decoding key-equations for Reed-Solomon codes can be derived systematically. These equations are always solved by the extended Euclidean algorithm.