Packet Reservation Multiple Access (PRMA) is emerging as a possible multiple access scheme for the forth-coming Personal Communication systems, due to its inherent flexibility and to its capability to exploit silence periods to perform a statistical multiplexing of traffic sources, often characterised by a high burstiness. On the other hand, the current trend in reducing cell sizes and the more complex traffic scenarios pose major planning problems, which are best coped with by adaptive allocation schemes. The identification of adaptive schemes suitable to operate on a shorter time scale, which is typical of packetised information, disclose a number of problems which are addressed in this paper. A viable solution is provided by a well-known self-adaptive assignment method (Channel Segregation), originally developed for FDMA systems, provided it is conveniently adapted for PRMA operation. Simulations show good performance, provided that values of some system variables are correctly chosen. These results encourage further studies in order to refine adaptive methods suitable for cellular, packet switched personal communications systems.

As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of the DRAM and its new pipeline architecture.

Ever increasing demand for higher bandwidth memories, which is fueled by multimedia and 3D graphics, seems to be somewhat satisfied with various emerging memory solutions. This paper gives a review of these emerging DRAM architectures and a performance comparison based on a condition to let the readers have some perspectives of the future and optimized graphics systems.

This paper describes the new α-particle induced soft error mechanism, the Minority Carrier Outflow (MCO) effect, which may seriously affect the reliability of the scaled DRAMs with three dimensional capacitors. The MCO chargge increases as the device size miniaturizes because of the three dimensional capacitor effect as below. As the device scales down, the storage node volume decreases which results in the higher minority carrier density in the storage node and larger outflow charge. Also as the device plan view miniaturizes, the stack capacitor height or trench depth does not scales down or even increases to keep the storage node capacitance, therefore the initially generated minority carrier becomes larger. A simple analytical MCO model is introduced to evaluate the MCO effect quantitatively. The model agrees well with the three dimensional device simulation. The MCO model predicts that the life time of the minority carrier in the storage node strongly affects the MCO charge, however, even when the life time is as small as the order of 100 ps, the MCO effect can be the major soft error mechanism.

With the foreseen growth of communication capacity, further capacity and flexibility enhancements are required for future transport networks. Photonic switching is expected to be a key technology to solve the potential bottleneck, which could be found in transport network nodes. This paper first explains the "Optical Fiber Freeway" concept, as an example of future transport networks. Following this, the possible optical transport network structure using photonic switching technologies, for realizing the Optical Fiber Freeway concept, is explained. An Optical CrossConnect (OXC) and optical Add/Drop Multiplexer (ADM) are key components. Examples of recent development of photonic switching systems toward these targets are also reviewed. An OXC using photonic Space-Division (SD) switching technology has been proposed and demonstrated. This type of OXC will realize flexible reconfiguration and optical hitless switching, and it can meet the introduction of Wavelength Division Multiplexing (WDM) technique. Line failure restoration operation at 2.4Gb/s has been successfully demonstrated. An optical packet network with a slotted ring/bus structure using a wavelength address technique has been proposed as a packet/cell based optical ADM. The experimental system employs a practical media access control system as well as a fast-wavelength switched transmitter suppressing thermally induced wavelength drift. Cell communication at 622Mb/s has been demonstrated with the experimental system. These results show that hardware technologies have been developed steadily. With a future study on an all optical network management scheme, a high capacity and flexible optical network would be realized.

A bipolar low-voltage multiplier core is presented. The proposed low-voltage multiplier core is built from a bipolar quadritail cell. Voltages applied to the individual bases of the transistors in the bipolar quadritail cell are aVxbVy, (a1)Vx(b1)Vy ,aVx(b1)Vy, and (a1)VxbVy, where Vx and Vy are the input signals, and a and b are constants, for example, VxVy, O, Vx, and Vy. Simple input systems using resistive dividers are also described. The dc transfer characteristics were verified on a breadboard using transistor-arrays and discrete components. The dc transfer characteristic of the proposed multiplier core is very close to that of the Gilbert multiplier cell, but the proposed multiplier core is operable on low supply voltage. Therefore, a bipolar multiplier core using a quadritail cell is a low-voltage version of the Gilbert multiplier cell. The proposed bipolar multiplier is practically useful because it can be easily implemented in integrated circuits by utilizing a multiplier core and a resistor-only input system, and it also operates at very lowvoltage. Therefore, the proposed bipolar multipliers are very suitable for low-power operation.

A 10-kW (53V/200A), forced-air-cooled DC-DC converter has been developed for fuel cell systems. This converter uses new high-voltage bipolar-mode static induction transistors (BSIT), a new driving method, a zero-voltage-switched pulse-width-modulation technique, and a new litz wire with low AC resistance. It weighs only 16.5kg, has a volume of 26,000cm3, operates at 40kHz, and has a power conversion efficiency of about 95%. The power loss of this converter is 20% less than that of conventional natural-air-cooled DC-DC converters, and the power density is 3 times as high.

With the development in portable electronic equipment, the demand for secondary batteries of high energy density is increasing. Recently, nickel metal hydride secondary batteries (Ni/MH) are expanding the market, and lithium ion secondary batteries have been newly developed and commercialized. This paper describes in detail Ni/MH and lithium ion secondary batteries, and reports on their development state and characteristics.

We propose a nonlocal impact ionization model applicable for the drain region where electric field increases exponentially. It is expressed as a function of an electric field and a characteristic length which is determined by a thickness of gate oxide and a source/drain junction depth. An analytical substrate current model for n-MOSFET is also derived from the new nonlocal impact ionization model. The model well explains the reason why the theoretical characteristic length differs from empirical expressions used in a pseudo two-dimensional model for MOSFET's. The nonlocal impact ionization model implemented in a device simulator demonstrates that the new model can predict substrate current correctly in the framework of drift-diffusion model.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

Memory type polymer dispersed liquid crystal (PDLC) can be applied to a thermal addressing display device cell. Making use of its easy fabrication of large area display using flexible film substrate, the PDLC film can be used as reusable paper for direct-view mode display. In this study, memory type PDLC cells are prepared with an aluminum reflector deposited onto one side of the substrate and the reflection property in the PDLC cell with the reflector is clarified and compared to that without the reflector in the off-, on- and memory-states. The increase of contrast ratio and the decrease of driving voltage can be concurrently realized by decreasing the cell thickness by attaching the reflector. In addition, the reflected light in the off-state is bright and colorless due to the reflector, as compared with the weak, bluish reflected light in the cell without the reflector. Reflected light in the on-state and the memory-state are tinged with blue.

A novel effective channel length extraction method has been developed, which utilizes the difference between the local threshold voltage of channel region and that of external region. In this method, the dependence of external resistance on Vg is taken into account, and it is not necessary to extract Vth. It is found that the external resistance can be approximated as the linear function of Vg with Vg around Vth. For a 0.4 µm gate length LDD MOSFET, the accuracy and resolution are estimated to be less than 0.02 µm and 0.003 µm, respectively.

A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.

We have developed a Virtual Playground," which allows various activities such as virtual playground and virtual visiting areas for hospitalized children who can not usually go outside. A Virtual Playground system is composed of TV monitors, joysticks, cameras, video transmission devices, and a graphics workstation. In a Virtual Playground environment, children can experience what is impossible or difficult during their stay in a hospital. We have completed a couple of experiments already and discussed its effects.* In our recent work, we also introduced a simple version of the Cave display to the Virtual Playground system.

A single-chip architecture for three-dimensional (3-D) computer graphics (CG) is discussed assuming portable equipment with a 3-D CG interface. Based on a discussion of chip requirements, an architecture utilizing DRAM technology is proposed. A 31-Mbit, on-chip DRAM cell array allows a full-color, 480640-pixel frame with two 3-D frame buffers for double buffering and one 2-D frame buffer for superimposed or background images. The on-chip pixel generator produces R, G, B, and Z data in a triangular polygon with a zigzag-scan interpolation algorithm. The on-chip frame synthesizer combines data from one of the 3-D buffers with that from the 2-D buffer to produce superimposed or background 2-D images within a 3-D CG image. Parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array provide a high data I/O rate. Estimation of the chip performance assuming the 0.35-µm CMOS design rule shows the chip size, the drawing speed, on-chip data I/O rate, and power dissipation would be 1413.5-mm, 0.25 million polygons/s, 1 gigabyte/s, and 590 mW at a voltage of 3.3 V, respectively. Based on circuit simulations, the chip can run on a 1.5-V dry cell with a drawing speed of 0.125 million polygons/s and a power dissipation of 61 mW. A scaled-down version of the chip which has an 1-kbit DRAM cell array with an attached alpha-blending circuit is being fabricated for evaluation.

Precise measurements of temperature dependence of the Andreev reflection current for the N–I–S junctions were carried out. Au and Pb were used as N (normal metal) and S (superconducting material), respectively. The experimental results agreed with the analyses based on the Arnold theory.

As a result of examination based on a newly available data set of millimeter-wave rain attenuation measured in the UK, it is found that the ITU-R specific rain attenuation model tends to appreciably underestimate millimeter-wave rain attenuation at frequencies above about 60GHz for the UK rain climate. This tendency is very similar to that previously reported for the Japanese experimental data at frequencies up to 245GHz. Furthermore, an alternative specific rain attenuation model based on the Japanese experimental data is found to be in fairly good agreement with the experimental data in the UK at frequencies up to 137GHz.

A globally and quadratically convergent algorithm is presented for solving nonlinear resistive networks containing transistors modeled by the Gummel-Poon model or the Shichman-Hodges model. This algorithm is based on the Katzenelson algorithm that is globally convergent for a broad class of piecewise-linear resistive networks. An effective restart technique is introduced, by which the algorithm converges to the solutions of the nonlinear resistive networks quadratically. The quadratic convergence is proved and also verified by numerical examples.

We present a method of extracting the digital inphase (I) and quadrature (Q) components from oversampled bandpass signals using narrow-band bandpass Hilbert transformers. Down-conversion of the digitized IF signals to baseband and reduction of the quantization noise are accomplished by the multistage decimator with the complex coefficient bandpass digital filters (BPFs), which construct the bandpass Hilbert transformers. Most of the complex coefficient BPFs in the multistage decimator can be replaced with the lowpass filters (LPFs) under some conditions, which reduces computational burden. We evaluate the signal to quantization noise ratio of the I and Q components for the sinusoidal input by computer simulation. Simulation results show that the equivalent amplitude resolution of the I and Q components can be increased by 3 bits in comparison with non-oversampling case.