We have developed a complete chromium oxide (Cr2O3) passivated gas tubing system by introducing ferritic stainless steel instead of conventional austenitic stainless steel (SUS316L). 100% Cr2O3 passivation film can be formed on electropolished ferritic stainless steel surface because the diffusion coefficient of Cr in ferritic stainless steel is 104 times larger than in austenitic stainless steel. In ferritic stainless steel, moreover, welded bead surface is covered by 100% Cr2O3 pas-sivated film by an introduction of advanced welding technology.

Circuit simulators are used to verify circuit functionality and to obtain detailed timing information before the expensive fabrication process takes place. They have become an essential CAD tool in an era of sub-micron technology. We have developed a new event-driven MOS circuit simulator to replace a direct method circuit simulator. In our simulator, partitioned subcircuits are analyzed by a direct method matrix solver, and these are controlled by an event-driven scheme to maintain accuracy. The key of this approach is how to manage events for circuit simulation. We introduced two types of events: self-control events for a subcircuit and prediction correcting events between subcircuits. They control simulation accuracy, and bring simulation efficiency through multi-rate behavior of a large scale circuit. The event-driven scheme also brings some useful functions which are not available from a direct method circuit simulator, such as a selected block simulation function and a batch simulation function for load variation. We simulated logic modules (buffer, adder, and counter) with about 1000 MOSFETs with our event-driven MOS circuit simulator. Our simulator was 5-7 times faster than a SPICE-like circuit simulator, while maintaining the less than 1% error accuracy. The selected block simulation function enables to shorten simulation time without losing any accuracy by selecting valid blocks in a circuit to simulate specified node waveforms. Using this function, the logic modules were simulated 13-28 times faster than the SPICE-like circuit simulator while maintaining the same accuracy.

A novel method has been developed to improve the dry etching selectivity of aluminum alloy with respect to photoresist by implanting ions into the patterned photoresist. The selectivity becomes 7.5, which is 5 times higher than that of the unimplanted case. Accordingly, this technology is very promising for fabricating multi-level interconnections in sub-half micron LSIs.

High-performance ULSI devices require ultraclean silicon surfaces, the complete removal of native oxides, and atomic level flatness and stabilization of the cleaned surfaces against molecular contaminants. Dry cleaning techniques are an attractive alternative to conventional wet processing for future ULSI production using cluster chambers or multi-process cham-bers. Organic contaminants, including photoresist polymers, are effectively removed by photo-excited ozone cleaning. We have found photo-excited halogen radicals to be useful for removing trace metals and native oxides from silicon surfaces without damaging on silicon and silicon-dioxide surfaces. We success-fully terminated hydrogen on (100) silicon surfaces by annealing in pure hydrogen ambient. A dry cleaning system with these sequential processes will be useful in constructing fully-integrated mass-production lines of high-performance ULSI devices.

The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

This letter describes an efficient and economical method for dropping optical fiber to residential premises in which several fiber ribbons in a distribution cable are assigned to one dropping point. The optical fiber cables for dropping, which contain mono-coated fibers, are then aerially installed between several poles from this point during initial construction. One or two fibers in a cable are then branched and dropped to a subscriber when the demand arises. When an optical drop wire stranded cable is used as the optical fiber cable for dropping, the above method can be employed without the need for a fiber joint in the dropping portion. The tube stranding pitch of this cable is investigated theoretically and experimentally, and the cable is manufactured based on the results. The transmission characteristics of the cable are confirmed to be stable.

A novel circuit design technique for realizing a linear CMOS transconductance element, consisting of an adaptively biased source-coupled differential pair using a quadritail cell, is proposed. In the circuitry, the quadritail cell, which provides an output current proportional to the square of a differential input voltage, cancels a nonlinear term of the source-coupled differential pair. The circuit have a superior linearity and a wide linear input voltage range compared with the conventional linear CMOS transconductance elements because the transconductance characteristic is theoretically linear over wide input voltage range when all the MOS field-effect transistors (MOSFETs) are operating in the saturation region and the MOSFETs' behaviors are according to the relation based on the square-law characteristic. The proposed adaptively biased source-coupled differential pair was verified by using transistorarrays and discrete components on a breadboard.

This paper presents a generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs). This approach relies on a structured walking-1 test set in the sense that a structural analysis based on the layout of the interconnect system, is carried out. The proposed structural test method differs from previous approaches as it explicitly avoids aliasing and confounding and is applicable to dense as well as sparse layouts and in the presence of faults in the programmable devices of a FPIC. The proposed method is applicable to both one-step and two-step test generation and diagnosis. Two algorithms with an execution complexity of O(n2), where n is the number of nets in the interconnect, are given. New criteria for test vector compaction are proposed; a greedy condition is exploited to compact test vectors for one-step and two-step diagnosis. For a given interconnect, the two-step diagnosis algorithm requires a number of tests as a function of the number of faults present, while the one-step algorithm requires a fixed number of tests. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. The applicability of the proposed approach to FPICs as manufactured by [1] is discussed and evaluated by simulation.

CAMs (Content Addressable Memories) are functional memories which have functions such as word-parallel equivalence search, bilateral 1-bit data shifting between consecutive words, and word-parallel writing. Since CAMs can be integrated because of their regular structure, massively parallel CAM functions can be executed. Taking advantage of CAMs, Ishiura and Yajima have proposed a parallel fault simulation algorithm using a CAM. This algorithm, however, requires a large amount of CAM storage to simulate large-scale circuits. In this paper, we propose a new massively parallel fault simulation algorithm requiring less CAM storage, and compare it with Ishiura and Yajima's algorithm. Experimental results of the algorithm on CHARGE --the CAM-based hardware engine developed in our laboratory--are also reported.

This paper describes a simulation technique of start-up characteristics that considers a nonlinearity of the drive level of quartz crystal resonators. A nonlinear resonator model for SPICE where the resonant resistance varies with the voltage added to a resonator is proposed. In an examination using a transistor Colpitts oscillator, the simulation using this technique agreed with the experimental results very well.

A vertical magnetoresistive (MR)/inductive head using the current bias technique has been developed for high-density magnetic recording. In this head, the sense current is orthogonal to the air-bearing surface (ABS). The area exposed at the ABS of the MR element is beneath the front lead, and the active area of the sensor is positioned behind that area. The MR element is composed of two permalloy films separated by a thin nonmagnetic material. The easy axis of the films is oriented parallel to the ABS and the films are magnetostatically coupled. The magnetic field created by the sense current is applied in the direction of the easy axis and the MR element is stabilized. In this head structure, no MR-element-stabilizing layer, such as an antiferromagnetic film or a hard magnetic film, is needed. Since the permalloy film beneath the front lead acts as a front flux guide, the signal flux propagates in the sensing area of the MR element behind the ABS. The new vertical MR head has the same electrical performance characteristics as the conventional horizontal MR head. The offtrack signal profile is symmetric against the track center because the magnetization of the two permalloy films rotates symmetrically in the signal-flux direction. The output signal level of this head is independent of the read trackwidth, which favors a narrow trackwidth. The exposed portion at the ABS is only connected to the common lead and is at ground potential. In this design, electrostatic breakdown does not occur and no corrosion is observed. Tests have shown that as the flying height is reduced, the error rate is reduced and noise does not increase. This head structure appears suitable for the near-contact recording of the near future.

We believe that virtual world communication will subsume BBS and visual communication. Accordingly, we proposed the networked virtual world "Interspace" for visual communication. If we are to achieve education and training in this world, techniques to receive and transmit information without any special training are necessary. The traditional "easy" ways of transmitting information are talking and drawing. In Interspace, users can already talk each other. In this paper we focus on drawing. In daily life we communicate through drawings in various situations. At this time it is important to recognize who is drawing and where the participants are watching. It is difficult to realize these functions using conventional media, but it is possible to realize them in virtual space. In virtual space, the system can clearly represent who is drawing and where participants are watching; expressing topics in virtual space frees us from many physical restrictions. In this paper we discuss the process of drawing when many participants share topics in virtual space; the necessary conditions for our system are considered. We design a system that offers functions to make drawing sheets, to display the view fields of participants, and to share visual fields. Furthermore, we propose the mode of InterSheet called "InterMirror" which shows mirror images of partners and their drawings. We make a prototype and evaluate it. The results indicate the synergistic effect of drawing with voice and the usefulness of drawing for communication in virtual space.

An exact solution of the propagation constant of a cylindrical waveguide has been obtained in the event of the conductivity of the waveguide-composing conductor being finite. The said analysis has been reduced to a problem to solve a transcendental equation concerning an eigenvalue of the individual modes of the in-guide electromagnetic wave, and calculation of Jn-1(z)/Jn(z) by using of Bessel function becomes necessary. With a large conductivity the absolute value of the complex number z becomes excessively large, and none of calculation method with high accuracy has been found with the aid of a computer. This paper has solved the problem by using a continued fraction for the calculation with regard to which a recurrence formula is utilized. With the TE01 wave that has conventionally been used as a millimeter-wave guide, it is cleared that it is sufficient to select the number of the calculation terms of the continued fraction to the extent of approximately 1000 in the accuracy in accordance with this calculation method. It is also cleared that the approximation solution obtained by a method of perturbation coincides with the exact solution for the conductivity σ 102 [S/m].

In this paper we propose a two-stage address coding scheme to transmit two data symbols at once within a frame in a MFSK/FH-CDMA system. We compare it with the conventional system using single-stage address coding. Assumed that the address codes of all users are known in the receiver. A multiuser detection scheme is applied and the performance is evaluated by computer simulations to show the improvement in bit error rate (BER) compairing to the conventional system. We also investigate the performance of error-correcting coding and decoding in the two-stage address coded MFSK/FH-CDMA system. An erasure decoding scheme is modified for the two-stage address coded system and is utilized to improve spectral efficiency or to increase user capacity in the MFSK/FH-CDMA system. Finally, we investigate a hybrid scheme of combining the multi-user detection scheme and the error-correcting decoding scheme for the two-stage address coded MFSK/FH-CDMA system. The performance is evaluated by computer simulations.

The use of existing metallic local line facilities is being studied for providing "video on demand (VOD)" services to residential subscribers across asymmetric digital subscriber lines (ADSL). ADSL carries a high-rate channel in the downstream direction from a central office (CO) to the subscriber, and a low-rate channel in both directions on an existing 2-wire pair. Audio and video signals are compressed by the moving picture experts group's standardized algorithms (MPEG 1 and MPEG 2), and delivered to the subscriber in the high-rate channel. Control (demand and response) signals are transceived in the low-rate channel. This paper presents the line length coverage of ADSL systems given the environment of NTT's local networks. The bit rates in the downstream and upstream directions are assumed to be 1.6-9.2Mbit/s and 24kbit/s, respectively. Two types of ADSL systems are considered: transceiving ADSL signals using the plain old telephone service (POTS) line or the basic rate access (BRA; 320 kbaud ping-pong transmission system) line on the same 2-wire pair. 16-QAM, 32-QAM and 64-QAM are compared as transmission schemes. Intra-system crosstalk interference (interference between identical transmission systems) and inter-system crosstalk interference (interference between different transmission systems) with the existing digital subscriber lines (DSL) are estimated. It is shown that the inter-system crosstalk interference with BRA is most stringent, and ADSL with 16-QAM yields the best performance in NTT's local networks. This paper concludes that realizing ADSL with 16-QAM can achieve channel capacities of up to 9.2Mbit/s for fiber-in-the-feeder (FITF) access systems, but the possibility of applying ADSL to direct access systems is remote except for a restricted short haul use. Some comparisons regarding American local networks are also described.

A computer-based system for the automatic determination of the physical parameters of rainfall was developed. The measuring device consists of a light source and two TV cameras. Images of raindrops that fell through the slit were observed on a frosted glass plate as shadow images which were photographed simultaneously by two TV cameras with different shutter speeds and analyzed. The data indicated that the shape of raindrops were spheroid in case of small diameter but were slightly deformed into an oblate spheroid in case of larger diameter, and the fall velocity tends to increase with increasing size of raindrops. Rainfall rates calculated from the shape and velocity were compared with those measured directly and found to agree.

This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.

Concerning the complexity of tree drawing, the following result of Supowit and Reingold is known: the problem of minimum drawing binary trees under several constraints is NP-complete. There remain, however, many open problems. For example, is it still NP-complete if we eliminate some constraints from the above set? In this paper, we treat tree-structured diagrams. A tree-structured diagrm is a tree with variably sized rectangular nodes. We consider the layout problem of tree-structured diagrams on Z2 (the integral lattice). Our problems are different from that of Supowit and Reingold, even if our problems are limited to binary trees. In fact, our set of constraints and that of Supowit and Reingold are incomparable. We show that a problem is NP-complete under a certain set of constraints. Furthermore, we also show that another problem is still NP-complete, even if we delete a constraint concerning with the symmetry from the previous set of constraints. This constraint corresponds to one of the constraints of Supowit and Reingold, if the problem is limited to binary trees.

NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm2, which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.