In this letter, we propose new driving methods for designing a driver independent of the current property of Organic Light Emitting Diodes (OLED) displays. The proposed methods are the Look-Up Table (LUT) and the Pulse Width Modulation (PWM). The LUT is used to handle the amount of the current for driving the OLED display panel and the PWM is applied to represent the gray scale on the OLED display panel. In particular, the proposed methods are used for the manufacturing of 1.8" 128 128 dot passive matrix OLED display panel. The designed circuit was fabricated using 0.6 µm, 2-poly, 3-metal CMOS process and applied to the Personal Communication System (PCS) phone successfully.

In this paper, we propose and evaluate a new channel assignment scheme for a micro-cellular network integrating data and conversational services. The channel assignment scheme combines handover processing depending on terminal speed with a preemptive scheme. High-speed terminals take over the channels of data terminals upon entering a full cell, while the data terminals are put in a queue until new resources are available. Simulating several variations of the scheme, allowing both fast moving data and voice terminals to preempt data terminals yielded the best result. Suspension time for fast moving data terminals was reduced dramatically, reducing the disadvantage caused by a high number of handovers. The cost was a small increase in blocking probability for new terminals.

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.

As technology moves to 600-1000 Gb/sq-in areal densities and deep sub-10 nm head-disk spacing, it is of crucial importance to prevent both the conventionally defined thermal decay and the tribologically induced decay of recorded magnetic signal. This paper reports a novel method for recording and visualizing the signature of the potential tribological decay. The details of the methodology, its working principles, and typical results obtained are presented in this work. The method is based on the introduction of a type of visualizing disks which use a layer of magneto-optical material with low Curie temperature to replace the magnetic layer used in the conventional magnetic media. The method and corresponding setup were used successfully in the visualization of potential decay caused by slider-particle-disk contact, slider-disk contact during track seeking operations, and slider-disk impact during loading and unloading operations.

The interaction between slider, lubricant and disk surface is becoming the most crucial robustness concern of advanced data storage systems. This paper reports comparative studies among various techniques for the measurement of head-disk spacing. It is noticed that the triple harmonic method gives a reading much closer to the reading of the head-disk spacing obtained optically at on-track center case, comparing with the PW50 method. Specially prepared disks with different carbon overcoat thickness (6.5 nm, 11 nm, 16 nm and 22 nm) were also used to study the reliability and repeatability of the triple harmonic method.

This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-µm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.

This paper presents an iterative algorithm for decoding product codes based on syndrome decoding of component codes. This algorithm is devised to achieve an effective trade-off between error performance and decoding complexity. A simplified list decoding algorithm, which uses a modified syndrome decoding method, for linear block codes is devised to deliver soft outputs for iterative decoding of product codes. By adjusting the size of the list, the decoder can achieve a proper trade-off between decoding complexity and performance. Compared to the other iterative decoding algorithms for product codes, the proposed algorithm has lower complexity while offers at least the same performance, which is demonstrated by analyses and simulations. The proposed algorithm has been simulated for BPSK and 16-QAM modulations over both the additive white Gaussian noise (AWGN) and Raleigh fading channels. This paper also presents an efficient scheme for applying product codes and their punctured versions. This scheme can be implemented with variable packet size and channel data block.

Recently, neural networks (NNs) have been extensively applied to many signal processing problem due to their robust abilities to form complex decision regions. In particular, neural networks add flexibility to the design of equalizers for digital communication systems. Recurrent neural network (RNN) is a kind of neural network with one or more feedback loops, whereas self-organizing map (SOM) is characterized by the formation of a topographic map of the input patterns in which the spatial locations (i.e., coordinates) of the neurons in the lattice are indicative of intrinsic statistical features contained in the input patterns. In this paper, we propose a novel receiver structure by combining adaptive RNN equalizer with a SOM detector under serious ISI and nonlinear distortion in QAM system. According to the theoretical analysis and computer simulation results, the performance of the proposed scheme is shown to be quite effective in channel equalization under nonlinear distortion.

An algorithm for augmenting a binary linear code is presented. The input to the code augmenting algorithm is (n,k,d) code C and the output is an (n,k*,d) augmented code C (k* k) satisfying C C and the Gilbert bound. The algorithm can be considered as an efficient implementation of the proof of Gilbert bound; for a given binary linear code C, the algorithm first finds a coset leader with the largest weight. If the weight of the coset leader is greater than or equal to the minimum distance of C, the coset leader is included to the basis of C.

This letter presents a new approach for obtaining the expected waiting time for packets under the drop-head (also called a drop-from-front) scheme for buffer management. The results show that the drop-head scheme is more effective in reducing queueing delays than the drop-tail scheme.

In this paper, we describe a novel technique to extract a polyhedral description from panoramic range data of a scene taken by a panoramic laser range finder. First, we introduce a reasonable noise model of the range data acquired with a laser radar range finder, and derive a simple and efficient approximate solution of the optimal fitting of a local plane in the range data under the assumed noise model. Then, we compute the local surface normals using the proposed method and extract stable planar regions from the range data by using both the distribution information of local surface normals and their spatial information in the range image. Finally, we describe a method which builds a polyhedral description of the scene using the extracted stable planar regions of the panoramic range data with 360 field of view in a polar coordinate system. Experimental results on complex real range data show the effectiveness of the proposed method.

A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2 4 GB/s at 4 macros. The process cost has been kept low by using VT-MOS circuit technology and taking advantage of a characteristic of dual-gate oxide process technology. A tRAC of 11.6 ns at 2.0 V is achieved using a 'pre-detect redundancy' circuit.

In this paper, we show that a priori probabilities of information bits can be incorporated into metrics for syndrome decoding. Then it is confirmed that soft-in/soft-out decoding is also possible for syndrome decoding in the same way as for Viterbi decoding. The derived results again show that the two decoding algorithms are dual to each other.

In this paper, a novel continuous complementary sliding control was proposed to improve the tracking performance given the available control bandwidth and the extend of parameter uncertainty. With this control law, the ultimate bound of tracking error was shown to be reduced at least by half, as compared with the conventional continuous sliding control. More strikingly, the proposed control can effectively improve the error transient response during the reaching phase. We presented a composite complementary sliding control scheme for a class of uncertain nonlinear systems including the nonlinear electrohydraulic position servo control system, which will be used as an illustrated example. Simulation results indicated exceptional good tracking performance to step and sine wave reference inputs can be obtained. In addition, the disturbance rejection property of the controller to single-frequency sinusoidal disturbances is also outstanding.

A voltage-mode universal biquadratic filter using single current-feedback amplifier (CFA), two capacitors and three resistors is presented. The new circuit has four inputs and one output and can realize all the standard filter functions, that is, lowpass, bandpass, highpass, notch and allpass filters, without changing the circuit topology. The use of only one current-feedback amplifier simplifiers the configuration.

An LCD Driver IC includes more than 300 buffer amplifiers on a single chip. The phase compensation capacitors (on-chip Miller capacitors) for the amplifiers are more than 1000 pF and occupy a large chip area. This paper describes a two-gain-stage amplifier in which an on-chip Miller capacitor is not used for phase compensation in an LCD Driver IC. In the proposed amplifier, phase compensation is achieved only by a newly introduced zero, which is formed by the load capacitance and a phase compensation resistor connected between the output of the amplifier and the capacitive load. Designs of the phase compensation resistor and the amplifier before compensation are discussed, considering a typical load capacitance range. The test chip was fabricated. The newly introduced zero successfully stabilized the amplifier. The chip area for the amplifier was reduced by 30-40%, compared with our previously reported one. The current consumption of the amplifier was only 5 µA. The experimental results of the fabricated test chip support that the proposed amplifier is suitable to an LCD driver IC with a smaller chip area.

In CDMA systems, power control strategy is the most important issue since the capacity of the system is only interference-limited. For a better understanding of the effects of Forward Link Power Control Strategy (FLPCS) on the outage probability in fading environments, this paper has presented a theoretical analysis of forward link in a CDMA cellular system by introducing the τ-th power of distance driven control strategy. Based on the power control, the capacity and outage probability of the system are estimated and discussed. In particular, we consider the impact of fading environments and investigate the "hole" phenomenon. Based on our numerical results, the "hole" points are at the upper bounds of where it is possible to ensure minimization of the maximum value of total Interference-to-Signal Ratio (ISR). At those upper bound points, at least, the power control strategy leads to approximately threefold the capacity compared to the case without power control strategy. It can be concluded that the forward link without power control strategy is a very heavy restriction for the capacity of the CDMA system, especially in environments of significant fading.

An effective spatial resolution enhancement method for distributed strain measurement by BOTDR is proposed. An optical fiber is glued to a structure by a length less than the spatial resolution defined by the pulse width, and the Brillouin spectrum of the light scattered from the glued optical fiber is investigated theoretically. The apparent strain xp observed in the fiber is found to be proportional to the accurate strain a. The ratio r=xp/a coincides with the ratio of the glued length to the spatial resolution. Spatial resolution as small as 0.2 m is demonstrated experimentally for small strains of less than 10-3.

Embedded-DRAM (eDRAM) power-energy estimation model is proposed for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improves the accuracy of the conventional SRAM power-energy models. The power-energy estimation using SSBA model shows 95% accuracy compared with the transistor level power simulation for three fabricated eDRAMs. The SSBA model combined with the high-level simulator provides fast and accurate system level power-energy estimation of eDRAM.

This paper investigates the stochastic property of packet destinations in order to describe Internet access patterns. If we assume a sort of stationary condition for the address generation process, the process is an LRU stack model. Although the LRU stack model gives appropriate descriptions of address generation on a medium/long time-scale, address sequences generated from the LRU stack model do not reproduce Zipf-type distributions, which appear frequently in Internet access patterns. This implies that the address generation behavior on a short time-scale has a strong influence on the shape of the distributions that describe frequency of address appearances. This paper proposes an address generation algorithm that does not meet the stationary condition on the short time-scale, but restores it on the medium/long time-scale, and shows that the proposed algorithm reproduces Zipf-type distributions.