This paper proposes a managed IP multicast platform that enables IP multicast services to be used for business. Nowadays, many business applications have switched from traditional network platforms to the IP platform. Among these applications, one-to-many or many-to -many types of applications are especially essential to business users. These applications may use IP Multicasting for transmitting data to many users. However, for business applications, it is difficult to use the present IP Multicast services, because they lack many requirements for business usage. The requirements are address management, authentication, time management, and guaranteed throughput. To satisfy the business users, we made the design of a managed IP multicast platform that will meet these requirements. Our platform, which separates the routing control layer and the packet forwarding layer, is called GMN-CL (Connection Technologies for Global Mega-media Network). The routing control layer manages routing information and controls network routing centrally, so it can understand the whole network situation and perform efficient routing. The packet forwarding layer can concentrate completely on forwarding, so the forwarding speed and copying speed is higher than when using routers. We have implemented our design of a managed IP multicast platform over GMN-CL. This paper reports the system design, implementation, and evaluation.

We propose a novel optical add/drop multiplexer (OADM) utilizing free spectral range (FSR) periodicity of an arrayed-waveguide multiplexer (AWG). In this OADM, wavelength-division multiplex (WDM) signal is multiplexed and/or de-multiplexed in two steps. Power penalty due to coherent crosstalk is drastically reduced compared with that of conventional OADM where AWG multiplexers are opposite to each other. The calculated power penalty due to the coherent crosstalk is about 0.7 dB after the 16 OADMs in the case of 128 wavelengths. It was confirmed through a computer simulation that more than one hundred channels at 10 Gbps data rate could be accommodated in an OADM network with 16 nodes. These results show that the OADM network with over 1 Tbps capacity and 16 nodes could be constructed.

A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m 714 µ m.

We propose a novel optical add/drop multiplexer (OADM) utilizing free spectral range (FSR) periodicity of an arrayed-waveguide multiplexer (AWG). In this OADM, wavelength-division multiplex (WDM) signal is multiplexed and/or de-multiplexed in two steps. Power penalty due to coherent crosstalk is drastically reduced compared with that of conventional OADM where AWG multiplexers are opposite to each other. The calculated power penalty due to the coherent crosstalk is about 0.7 dB after the 16 OADMs in the case of 128 wavelengths. It was confirmed through a computer simulation that more than one hundred channels at 10 Gbps data rate could be accommodated in an OADM network with 16 nodes. These results show that the OADM network with over 1 Tbps capacity and 16 nodes could be constructed.

In this paper, we proposed two models, the full multiple MCS (Multicast Server) model and the hybrid multiple MCS model to support multiple MCS over a single large cluster in ATM (Asynchronous Transfer Mode) networks. Also, we presented two methods for MCS assignment which are known as 2PSPMT (2 Phase Shortest Path based on Multicast tree) and hybrid-2PSPMT, and evaluated its performance by simulation. When an ATM host requests joining a specific multicast group, the MARS (Multicast Address Resolution Server) designates a proper MCS among the multiple MCSs for the group member to minimize the average path delay between the sender and the group members. Each method for MCS assignment construct a 2-phase partial multicast tree based on the shortest path algorithm. We reduced the average path delay in the multicast tree using these methods with various cluster topologies and MCS distribution scenarios in addition to distributing the load among multiple MCSs.

We consider the problem of efficient learning of probabilistic concepts (p-concepts) and more generally stochastic rules in the sense defined by Kearns and Schapire and by Yamanishi. Their models extend the PAC-learning model of Valiant to the learning scenario in which the target concept or function is stochastic rather than deterministic as in Valiant's original model. In this paper, we consider the learnability of stochastic rules with respect to the classic 'Kullback-Leibler divergence' (KL divergence) as well as the quadratic distance as the distance measure between the rules. First, we show that the notion of polynomial time learnability of p-concepts and stochastic rules with fixed range size using the KL divergence is in fact equivalent to the same notion using the quadratic distance, and hence any of the distances considered in [6] and [18]: the quadratic, variation, and Hellinger distances. As a corollary, it follows that a wide range of classes of p-concepts which were shown to be polynomially learnable with respect to the quadratic distance in [6] are also learnable with respect to the KL divergence. The sample and time complexity of algorithms that would be obtained by the above general equivalence, however, are far from optimal. We present a polynomial learning algorithm with reasonable sample and time complexity for the important class of convex linear combinations of stochastic rules. We also develop a simple and versatile technique for obtaining sample complexity bounds for learning classes of stochastic rules with respect to the KL-divergence and quadratic distance, and apply them to produce bounds for the classes of probabilistic finite state acceptors (automata), probabilistic decision lists, and convex linear combinations.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

A new CMOS DC voltage doubler with nonoverlapping switching control is proposed, in order to eliminate the dynamic current loss during switching as well as the threshold voltage drop of the serial switches. The simulated results at 1.5 V show that the maximum power efficiency is improved with about 30%, whereas the efficiency in the low output current region is larger than 5 times compared to the conventional voltage doublers. This proposed CMOS DC voltage doubler can be used as a VPP generator of low voltage DRAM's.

A 3 to 5-GHz Si-bipolar quadrature modulator and demodulator are described. Both feature a wideband frequency-doubling 90-degree phase shifter that has a mechanism for self-correction of phase errors caused by an original 90-degree phase-shift network at the half frequency of the carrier. Therefore, the phase shifter produces accurate quadrature carrier signals with doubled frequency. The quadrature modulator and demodulator in 30-GHz Si bipolar technology dissipate 80 mA at a 3-V supply. Image rejection of the modulator is more than 40 dB between 3.2 to 5.2 GHz. The phase and amplitude errors of the demodulator are less than 1.5 degrees and less than 0.15 dB, respectively, between 3.5 to 5.2 GHz. Therefore, both are suitable for either direct conversion or image-rejection transceivers for 5-GHz applications.

This paper examines similarities between the Decision Diffie-Hellman (DDH) assumption and the Quadratic Residuosity (QR) assumption. In addition, we show that many cryptographic protocols based on the QR assumption can be reconstructed using the DDH assumption.

We formalize a model of "demonstration of program result-correctness," and investigate how to prove this fact against possible adversaries, which naturally extends Blum's theory of program checking by adding zero-knowledge requirements. The zero-knowledge requirements are universal for yes and no instances alike.

We present a digital double relaxation oscillation SQUID (DROS) with a digital flux-locked-loop (FLL) circuit consisting of an up/down counter and a digital-to-analog (D/A) converter. The up/down counter was designed using 4 jucntion logic (4JL) gates operated with a 2-phase power system. The D/A converter was designed using an R-2R ladder-type D/A converter. We simulated the dynamic behavior of the digital DROS with a digital FLL circuit combined with the 5-bit ripple up/down counter and the D/A converter. Simulation results show correct flux-locked behavior and a high slew rate of 107Φ0/s for the digital DROS.

We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.

Debye's asymptotic series is frequently used for calculation of cylindrical functions. However, it seems that until now this series has not been used in all-purpose programs for numerical calculation of the cylindrical functions. The authors attempt to develop these all-purpose programs. We present some improvements for the numerical calculation. As the results, Debye's series can be used for the all-purpose programs, and it is found out that the series gives sufficient accuracy if some conditions are satisfied.

CAM (Content Addressable Memory) units are generally designed so that they can be applied to variety of application programs. However, if a particular application runs on CAM units, some functions in CAM units may be often used and other functions may never be used. We consider that appropriate design for CAM units is required depending on the requirements for a given application program. This paper proposes a CAM processor synthesis system based on behavioral descriptions. The input of the system is an application program written in C including CAM functions, and its output is hardware descriptions of a synthesized processor and a binary code executed on it. Since the system determines functions in CAM units and synthesizes a CAM processor depending on the requirements of an application program, we expect that a synthesized CAM processor can execute the application program with small processor area and delay. Experimental results demonstrate its efficiency and effectiveness.

A novel technique is developed to reconstruct a nonuniform transmission line by using arbitrary incident waveforms. By discretizing both the incident and reflected waves, we find that the ratio of reflected wave to incident wave has the same form as the reflection coefficient obtained by treating a nonuniform line as a cascaded, multiple-section signal line. A reconstruction scheme is derived to get the impedance profile of a nonuniform line. Some examples are presented to illustrate this new technique.

A new timing estimation algorithm for asynchronous DS/CDMA multiuser communication system is proposed in this paper. The algorithm is based on the Minimum Variance Distortionless Response (MVDR) beamforming technique that minimizes the beamformer's output power with the constraint that only the signal with exact timing is distortionlessly passed. Exploiting the characteristics that the MVDR beamformer's output power is severely degraded according to erroneous timing estimation, we develop an efficient algorithm to estimate each user's timing by scanning the beamformer's output power variation. Compared to the maximum a posteriori (MAP) or maximum likelihood (ML) based multiuser timing estimator, the complexity is extensively reduced by separating the multi-dimensional optimization problem into several one-dimensional optimization problems. Furthermore, the algorithm is computationally feasible than the subspace-based timing estimator since no eigendecomposition (EVD) is required. Moreover, the proposed algorithm is near-far resistant since the MVDR beamformer is inherently energy independent to the interferers.

This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high on-chip memory bandwidth attainable on merged DRAM/logic LSIs by replacing a whole large cache line in one cycle. At the same time, it attempts to avoid frequent evictions by decreasing the cache-line size when programs have poor spatial locality. Activating only on-chip DRAM subarrays corresponding to a replaced cache-line size produces a significant energy reduction. In our simulation, it is observed that our proposed on-chip memory-path architecture, which employs a direct-mapped D-VLS cache, improves the ED (Energy Delay) product by more than 75% over a conventional memory-path model.

A "dual-ring" network configuration is proposed in wavelength-division multiplexing (WDM) metropolitan area network (MAN). In the proposed architecture, a "sub-ring" using two fibers is added to the existing metropolitan WDM ring for flexible and cost effective addition of new nodes.

The non-collision packet reservation multiple access (NC-PRMA) protocol has been proposed for wireless voice communications. In that protocol, although it can avoid any collision by using control minislot, the terminal which generates its talkspurt in a current frame has to wait till a next frame to transmit an asking packet to obtain reservation. Furthermore, under integrated voice and data traffic, in the conventional NC-PRMA the voice packet dropping probability becomes worse, because of the number of slots that voice terminals can access are limited. In this paper, we propose the NC-PRMA with random transmission to idle slots. First, we evaluate the mean access delay and the voice packet dropping probability under only voice traffic by the theoretical analysis and the computer simulation. It is shown that the proposed scheme attains lower mean access delay than the conventional NC-PRMA. Next, we evaluate the data packet delay and the voice packet dropping probability under integrated voice and data traffic by the computer simulation. It is shown that the proposed scheme attains lower packet dropping probability than the PRMA and the conventional NC-PRMA.