This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW.

An optical fiber line testing system is essential for reducing maintenance costs and improving service reliability in optical access networks. NTT has already developed such a system called AURORA (AUtomatic optical fibeR opeRAtions support system). As we already use the 1310 and 1550nm wavelengths for communication, we use the 1650nm wavelength for maintenance testing in accordance with ITU-T recommendation L.41. Recently, a long wavelength band (L-band) that extends to 1625nm has begun to be used for WDM transmission. With a view to monitoring optical fiber cables transmitting L-band communication light, an attractive way of separating the U-band wavelength of the test lights from the L-band wavelength of the communication light is to use a chirped fiber Bragg grating (FBG) filter because of its steep optical spectrum. However, it is difficult to measure fiber characteristics with an optical time-domain reflectometer (OTDR), because multi-reflections appear in the OTDR trace when FBG filters are installed at both ends of an optical fiber line. In this paper, we consider this problem and show that the reflection loss at the port of a test access module (TAM) must be more than 36.6dB. We also describe the system design for an extended optical fiber line testing system using an L/U-band optical coupler, which has two chirped FBGs between two 4-port circulators for L-band WDM transmission. In this system, the reflection loss at a TAM port was 38.1dB, and we confirmed that there was no degradation in the OTDR trace caused by multi-reflections at the optical filters.

Content addressable memory (CAM) is one of the functional memories which realize word-parallel equivalence search. Since a CAM unit is generally used in a particular application program, we consider that appropriate design for CAM units is required depending on the requirements for the application program. This paper proposes a hardware/software cosynthesis system for CAM processors. The input of the system is an application program written in C including CAM functions and a constraint for execution time (or CAM processor area). Its output is hardware descriptions of a synthesized processor and a binary code executed on it. Based on the branch-and-bound method, the system determines which CAM function is realized by a hardware and which CAM function is realized by a software with meeting the given timing constraint (or area constraint) and minimizing the CAM processor area (or execution time of the application program). We expect that we can realize optimal CAM processor design for an application program. Experimental results for several application programs show that we can obtain a CAM processor whose area is minimum with meeting the given timing constraint.

Counting the number of points of Jacobian varieties of hyperelliptic curves over finite fields is necessary for construction of hyperelliptic curve cryptosystems. Recently Gaudry and Harley proposed a practical scheme for point counting of hyperelliptic curves. Their scheme consists of two parts: firstly to compute the residue modulo a positive integer m of the order of a given Jacobian variety, and then search for the order by a square-root algorithm. In particular, the parallelized Pollard's lambda-method was used as the square-root algorithm, which took 50CPU days to compute an order of 127 bits. This paper shows a new variation of the baby step giant step algorithm to improve the square-root algorithm part in the Gaudry-Harley scheme. With knowledge of the residue modulo m of the characteristic polynomial of the Frobenius endomorphism of a Jacobian variety, the proposed algorithm provides a speed up by a factor m, instead of in square-root algorithms. Moreover, implementation results of the proposed algorithm is presented including a 135-bit prime order computed about 15 hours on Alpha 21264/667 MHz and a 160-bit order.

WASMII is a virtual hardware system that executes dataflow algorithms using a dynamically reconfigurable multi-context device with a data driven control mechanism. Although the effectiveness of the system has been evaluated through simulations and using an emulator, implementation of WASMII was infeasible due to the unavailability of such a device. However, the first prototype of a practical dynamically reconfigurable multi-context device called DRL has been developed by NEC, and we developed a reconfigurable test bed using four sample DRL chips. On this board, we have implemented and executed some simple applications of WASMII mechanism. Evaluation results show that the performance of the parallel implementation of WASMII is almost twice as that of a PC with a CPU based on the corresponding technology.

In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 32 network connections, is designed on a chip (4.73mm 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.

A high-speed 32-bit RISC microcontroller has been developed. In order to realize high-speed operation with minimum hardware resource, we have developed new design and analysis methods such as a clock distribution, a bus-line layout, and an IR drop analysis. As a result, high-speed operation of 400 MHz has been achieved with power dissipation of 0.96 W at 1.8 V.

This paper describes an Embedded DRAM Hybrid Macro, which supports various memory specifications. The eDRAM module generator with Hybrid Macro provides more than 120,000 eDRAM configurations. This eDRAM includes a new architecture called Auto Signal Management (ASM) architecture, which automatically adjusts the timing of the control signals for various eDRAM configurations, and reduces the design Turn Around Time. An Enhanced-on-chip Tester performs the maximum 512b I/O pass/fail simultaneous judgments and the real time repair analysis. The eDRAM testing time is reduced to about 1/64 of the time required using the conventional technique. A test chip is fabricated using a 0.18 µm 4-metal embedded DRAM technology, which utilizes the triple-well, dual-Tox, and Co salicide process technologies. This chip achieves a wide voltage range operation of 1.2 V at 100 MHz to 1.8 V at 200 MHz.

The alternative c-means algorithm has recently been presented by Wu and Yang for robust clustering of data. In this letter, we analyze the convergence of this algorithm by transforming it into an equivalent form with the Legendre transform. It is shown that this algorithm converges to a local optimal solution from any starting point.

In this paper, we propose a TCAD driven hot carrier reduction methodology of 3.3 V I/O pMOSFETs design. The hot carrier reliability of surface channel I/O pMOSFET having drain structure in common with core devices has a critical issue. It is substantially important for the high-reliability devices to reduce both drain avalanche and channel hot hole components. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and drive current (ION), SDE/HALO of both core and I/O transistors can be totally optimized for reduction of process-steps and/or photo-masks.

Small-size MOSFETs are becoming core devices in RF applications because of improved high frequency characteristics. For reliable design of RF integrated circuits operating at the GHz range, accurate modeling of small-size MOSFET characteristics is indispensable. In MOSFETs with reduced gate length (Lg), the lateral field along the MOSFET channel is becoming more pronounced, causing short-channel effects. These effects should be included in the device modeling used for circuit simulation. In this work, we investigated the effects of the field gradient in the gate-drain capacitance (Cgd). 2-Dimensional (2D) simulations done with MEDICI show that the field gradient, as it influences the channel condition, induces a capacitance which is visible in the MOSFET saturation operation. Changes in Cgd is incorporated in the modeling by an induced capacitance approach. The new approach has been successfully implemented in the surface-potential based model HiSIM (Hiroshima-university STARC IGFET Model) and is capable of reproducing accurately the measured Cgd-Lg characteristics, which are particularly significant for pocket-implant technology. Results show that pocket-implantation introduces a steep potential increase near the drain region, which results to a shift of the Cgd transition region (from linear to saturation) to lower bias voltages. Cgd at saturation decreases with Lg due to steeper surface potential and increased impurity concentration effects at reduced Lg.

We use the Monte Carlo method to simulate electron transport in a zig-zag single-walled carbon nanotube with a wrapping index of n=10. Results show large low-field mobility, negative differential mobility, and large peaks in the drift velocity reaching 3.5107 cm/s.

In this work it is shown for the first time how to calculate in advance by momentum-based noise simulation for stationary Monte Carlo (MC) device simulations the CPU time, which is necessary to achieve a predefined error level. In addition, analytical expressions for the simulation-time factor of terminal current estimation are given. Without further improvements of the MC algorithm MC simulations of small terminal currents are found to be often prohibitively CPU intensive.

The validity of the expression for the electron energy flux is evaluated by using the Monte Carlo simulation. The drift, divergence, and scattering terms are directly calculated from changes in the physical values of particles. Each term composing the momentum and energy conservation equations can be reproduced by indirect calculation of the expression for the term that is a function of other physical values. However, it is found that a parameter in electron heat conductivity has to be adjusted to reproduce the direct calculation of the energy flux. Namely, the parameter of the Wiedemann-Franz law for heat conductivity should be chosen so that the underestimations of the drift and diffusion terms in the energy flux equation cancel each other. It is shown that the parameter influences the electron temperature in a 50-nm gate nMOSFET.

A simple address indexing method is proposed for path memory management in multi-PE Viterbi decoder, which solves data read/write conflict problem completely. This method not only simplifies control and addressing overhead but also has the advantage of requiring only two memory banks regardless of the number of PE's, with 100% PE utilization.

In this paper, a new narrowband beamformer with derivative constraint is developed for wideband and coherent jammers suppression. The so-called IQML algorithm with linear constraint, which is used to estimate the unknown directions of the jammers in signal-free environment, is shown to be an inappropriate constraint estimator. In this paper, a new IQML algorithm with a norm constraint is considered, which is a consistent estimator and can be used to achieve desired performance. It can be also employed in the CDMA system for MAI suppression. We show that it outperforms the approach with the linear constraint used in the narrowband beamformer, in terms of directional pattern, output SINR and nulling capability for wideband and coherent jammers suppression.

A large part of our daily lives is spent surrounded by buildings and other structures. In this paper, we used an infinitelength, multilayered cylindrical model to rigorously analyze the microwave specific absorption rate (SAR) of a human standing near a 90corner wall. At frequencies above 1 GHz, the interactions between the microwaves, the human body (including layer resonance), and the corner cause complex changes in the average SAR. We have shown numerically that the SAR with a corner present is up to four times larger than when there is no corner, and that the average SAR of TE waves at frequencies below 1 GHz is up to 10 times greater than when there is no corner.

TCP congestion control is receiving increased attention in recent years due to their usefulness for network stability, robustness use of network buffer and bandwidth resources on an end-to-end per-connection basis. The RED scheme was designed for a network where a single dropped packet is sufficient to signal the presence of congestion to the TCP protocol. This paper applies matrix-analytic approach to analyze both the long-term and the short-term drop behaviors of a queue with RED scheme and uses this model to quantify the benefits brought about by RED. The result shows that the drop probability between RED and Drop-Tail is very close under heavy load conditions. This indicates that RED not only can resolve the synchronization problem but also has the same loss performance with Drop-Tail scheme under the heavy load circumstances. Our findings also show that the rate oscillation behavior of RED is better than Drop-Tail when TCP applies the additive-increase and multiplication-decrease mechanism. As a consequence, it can help reduce the required buffer capacity in the RED router.

A three inputs and single output voltage-mode universal biquadratic filter using only two operational transconductance amplifiers (OTAs) and two capacitors is presented. The new circuits offer several advantages, such as employing the minimum number of active and passive components (two OTAs and two capacitors), the versatility to synthesize highpass, bandpass, lowpass, notch and allpass responses without component matching conditions, high input impedance for bandpass and lowpass filter realizations and good sensitivities performance.

This paper describes a method for assessing the structural integrity of International America's Cup Class (IACC) yachts using a fiber optic distributed strain sensor. IACC yachts are made of advanced composite materials designed for high stiffness and lightness, however, a number of critical accidents have occurred during sailing. So we developed a health monitoring system and applied it to two Japanese IACC yachts to measure the distributed strain by using an optical fiber sensor installed in their hulls. We then estimated the three-dimensional distributed strain and compared the results with simulated data obtained by finite element analysis (FEA) to confirm the designed strength of these yachts.