Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.

A two-phase boosted voltage (VPP) generator circuit was proposed for use in giga-bit DRAMs. It reduced the maximum gate oxide voltage of pass transistor and the lower limit of supply voltage to VPP and VTN respectively while those for the conventional charge pump circuit are VPP+VDD and 1.5 VTN respectively. Also the pumping current was increased in the new circuit.

The layer3 switch enables us to fast transmit IP datagrams using the cut-through technique. The current layer3 router would become bottleneck in terms of delay performance as the amount of traffic injected into high speed networks gets relatively large. Thus, the layer3 switch should be an important element constructing the next generation Internet backbone. In this paper, we analyze the cut-through rate, the datagram waiting time and the mis-ordered rate of a layer3 switch in case of flow-driven connection setup. In the analysis, by using 3-state Markov modulated Bernoulli process (MMBP), we model the arrival process of IP flow and IP datagram from each source. Furthermore, we investigate impacts of the arrival rate and the average datagram length on the performance.

The applications of reactance-loaded beam tilting dipole antennas have been reported by many researchers. The reactance elements loaded on the applications reported up to date have been used only for the purpose of beam tilting. This paper presents the basic characteristics of the beam tilting dipole antenna element in which one reactance element is used for the impedance matching at the feed point. The radiation pattern is tilted by the properly determined driving point position, and the loading reactance is used to obtain forced resonance without great changes in tilt angle. The numerical results demonstrate that the reactance element should be loaded in the region where the driving point is placed to obtain forced resonance of the antenna with little changes in beam tilt angle. In case the proposed forced resonant beam tilting antenna with 0.8λ length is driven at 0.2λ from the center, the main beam tilt angle of 57.7 degrees, the highest power gain of 8.6 dB, and VSWR=2.2 are obtained.

Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.

In this paper, the Linear Exponential Quadratic Gaussian with Loop Transfer Recovery (LEQG/LTR) methodology is employed for the design of high performance induction motor servo systems. In addition, we design a speed sensorless induction motor vector controlled driver with both the extended Kalman filter and the LEQG/LTR algorithm. The experimental realization of an induction servo system is given. Compared with the traditional PI and LQG/LTR methods, it can be seen that the system output sensitivity for parameter variations and the rising time for larger command input of the proposed method can be significantly reduced.

Hallen's integral equation for cylindrical antennas is modified to deal with finite gap excitation. Because it is based on more realistic modeling, the solution is more accurate, and the convergence is guaranteed. The new equation is written with a new excitation function dependent on the gap width. The moment method analysis is presented where the piecewise sinusoidal surface current functions are used in Galerkin's procedure. Total, external and internal current distributions can be determined. Numerical results for cylindrical antennas with wide variety of gap width and radius are shown, and are compared with the numerical results by the Pocklington type integral equation and those by measurement.

We investigated the reflection of light caused by sharp bends in optical fiber experimentally. The position distribution of reflection power was measured using an OTDR and an OLCR. We found that the reflection power increased linearly as the logarithm of the bending loss increased, which agrees with expectation from a simple theoretical model. We believe that the light we observed was part of the leaked light, which was reflected between the primary and secondary coatings.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.

The optimum bias point for a drain mixer operating on low local oscillator (LO) power was investigated. The bias voltage dependence of the required LO power and the conversion gain in the drain mixer was clarified by a simplified nonlinear model which the drain current characteristics around knee voltage is approximated by two straight line segments. It was found that an optimum gate bias voltage Vgs exists for a given applied LO power, and the optimum gate bias voltage moves toward the pinch-off voltage as the injection LO power level decreases. In order to verify the variation of the optimum gate bias voltage, a 60 GHz MMIC drain mixer adopting the optimum gate bias voltage for low LO power level was fabricated. The fabricated drain mixer exhibited a conversion gain of 0 dB with the injection LO power level of 0 dBm. This value of 0 dBm is the best performance yet obtained for a 60 GHz MMIC drain mixer. The measured optimum gate bias voltage was near the pinch-off voltage. This result was in good agreement with the theoretical analysis. The LO power level of a drain mixer has been improved so that it is on a par with that of a gate mixer.

Newer off-chip DRAM families, including Synchronous DRAMs (SDRAMs) and RAMBUS DRAMs (RDRAMs), are becoming standard choices for the design of high-performance systems. Although previous work in High-Level Synthesis (HLS) has addressed exploiting features of page-mode DRAMs, techniques do not exist for exploiting the two key features of these newer DRAM families that boost memory performance and help overcome bandwidth limitations: (1) burst mode access, and (2) interleaved access through multiple banks. We address pre-synthesis optimizations on the input behavior that extract and exploit the burst mode and multiple bank interleaved access modes of these newer DRAM families, so that these features can be exploited fully during the HLS trajectory. Our experiments, run on a suite of memory-intensive benchmarks using a contemporary SDRAM library, demonstrate significant performance improvements of up to 62.5% over the naive approach, and improvements of up to 16.7% over the previous approach that considered only page-mode or extended-data-out (EDO) DRAMS.

In this paper, we show that the principle of quantum cryptography can be applied not only to a key distribution scheme but also to a data transmission scheme. We propose a secure data transmission scheme in which an eavesdropping can be detected based on sharing the bases Alice (the sender) and Bob (the receiver) have. We also show properties of this scheme.

A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.

A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a very high-speed and low-power memory system that also includes refresh-free, compact RTD-based memory cells. By combining RTDs with n-type transistors of conventional complementary metal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) family of logic circuits, having very low power-delay product and good noise immunity, has recently been developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly 20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stability analysis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable and unstable states which are closely related to the I-V characteristics of the RTDs. The paper also analyzes in details the refresh-free memory cell design, known as tunneling static random access memory (TSRAM). The innovative cell design adds a stack of two RTDs to the conventional one-transistor dynamic RAM (DRAM) cell and thereby the cell can indefinitely hold its charge level without any further periodic refreshing. The analysis indicates that the TSRAM cell can achieve about two orders of magnitude lower stand-by power than a conventional DRAM cell. The paper demonstrates that RTD-based circuits hold high promises and are likely to be the key candidates for the future high-density, high-performance and low-power memory systems.

A 32-bit motor-drive-specific microcontroller chip was newly designed, implemented using a 0.8 µm double-metal CMOS process, and its feasibility was successfully tested by applying the fabricated microcontroller chip to a real AC induction motor drive system. The microcontroller chip includes a single-precision floating-point unit, peripheral devices for motor drive, and a memory controller as well as the SPARC V7 CPU. The pipeline scheme and the two-step multiplication method were used in the multiplier of floating-point unit for the best area and speed trade-off, using the standard cell library available for the design. The chip size is 12.7 12.8 mm2, the number of transistors is around 562,000, and the power consumption is 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz. Both a standard cell library and a full-custom layout were used in the implementation.

This paper discusses global area optical transport ring networks using wavelength division multiplexing (WDM) technologies and proposes a novel optical add/drop multiplexer (OADM) architecture suitable for such an application field. Study on the requirements of a global area ring application elucidates the appropriate ring/protection architecture as the path switched bi-directional ring. The proposed OADM architecture has flexibility in terms of path provisioning and scalability. We conclude that the proposed OADM can effectively configure the large-scale path switched bi-directional rings.

An optical add-drop multiplexer with a grating-loaded directional coupler in silica waveguides is demonstrated. The device for this configuration has a large fabrication tolerance and is small in size. A new scheme, in which the coupling length of the directional coupler is twice the complete coupling length, enables low cross-talk for both add and drop operations. This device is polarization-independent due to its relatively low-temperature process.

This paper discusses global area optical transport ring networks using wavelength division multiplexing (WDM) technologies and proposes a novel optical add/drop multiplexer (OADM) architecture suitable for such an application field. Study on the requirements of a global area ring application elucidates the appropriate ring/protection architecture as the path switched bi-directional ring. The proposed OADM architecture has flexibility in terms of path provisioning and scalability. We conclude that the proposed OADM can effectively configure the large-scale path switched bi-directional rings.

An optical add-drop multiplexer with a grating-loaded directional coupler in silica waveguides is demonstrated. The device for this configuration has a large fabrication tolerance and is small in size. A new scheme, in which the coupling length of the directional coupler is twice the complete coupling length, enables low cross-talk for both add and drop operations. This device is polarization-independent due to its relatively low-temperature process.

A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing memory latency and improving memory bandwidth. In this paper we evaluate the performance of a single chip multiprocessor integrated with DRAM when the DRAM is organized as on-chip main memory and as on-chip cache. We compare the performance of this architecture with that of a more conventional chip which only has SRAM-based on-chip cache. The DRAM-based architecture with four processors outperforms the SRAM-based architecture on floating point applications which are effectively parallelized and have large working sets. This performance difference is significantly better than that possible in a uniprocessor DRAM-based architecture, which performs only slightly faster than an SRAM-based architecture on the same applications. In addition, on multiprogrammed workloads, in which independent processes are assigned to every processor in a single chip multiprocessor, the large bandwidth of on-chip DRAM can handle the inter-access contention better. These results demonstrate that a multiprocessor takes better advantage of the large bandwidth provided by the on-chip DRAM than a uniprocessor.