We have applied hot-carrier circuit-level simulation to memory peripheral circuits of a few thousand to over 12K transistors using a simple but accurate degradation model for reliability verification of actual memory products. By applying simulation to entire circuits, it was found that the location of maximum degradation depended greatly upon circuit configuration and device technology. A design curve has been developed to quickly relate device-level DC lifetime to circuit-level performance lifetime. Using these results in conjunction with a methodology that has been developed to predict hot-carrier degradation early in the design cycle before TEG fabrication, accurate total-circuit simulation is applied early in the design process, making reliability simulation a crucial design tool rather than a verification tool as technology advances into the deep sub-micron high clock rate regime.

Degradation of ferroelectricity in PZT (Pb(Zr0. 52, Ti0. 48)O3) thin-film capacitors caused by heat treatment in a reductive ambience is investigated. We have found that the degradation of ferroelectricity depends upon the metal used for the top electrode of the PZT capacitor. The increased degradation in the case of a PZT capacitor with Pt electrodes can be explained by a catalytic reaction on the Pt surface. With the use of an IrO2 non-catalytic top electrode, we have made the ferroelectricity of an IrO2/PZT/Pt capacitor retained even after the H2 annealing at 400, or above.

The tape deformation due to such particles as wear debris and dust in the head/tape contact region is one of the main causes of the signal quality deterioration in magnetic tape devices. Thus it is significant to make clear the tape deformation due to a particle for realizing higher recording densities. This paper investigates the tape deformation profile generated by a particle through an interferometric experiment and a simulation using a point loaded tape model. A rather good agreement between them is obtained, thereby the simulation is verified appropriate to estimate the tape deformation due to a particle. This paper also describes the relationship between the spacing loss and the particle height, considering the tape deformation profile obtained from the simulation. In addition, the influence of the particle height on the width of the tape deformed area is estimated, which can make a basis of the design of error correction code.

We discuss the uniqueness of 3-D shape reconstruction of a polyhedron from a single shading image. First, we analytically show that multiple convex (and concave) shape solutions usually exist for a simple polyhedron if interreflections are not considered. Then we propose a new approach to uniquely determine the concave shape solution using interreflections as a constraint. An example, in which two convex and two concave shapes were obtained from a single shaded image for a trihedral corner, has been given by Horn. However, how many solutions exist for a general polyhedron wasn't described. We analytically show that multiple convex (and concave) shape solutions usually exist for a pyramid using a reflectance map, if interreflection distribution is not considered. However, if interreflection distribution is used as a constraint that limits the shape solution for a concave polyhedron, the polyhedral shape can be uniquely determined. Interreflections, which were considered to be deleterious in conventional approaches, are used as a constraint to determine the shape solution in our approach.

The structure of bidirectional syndrome decoding for binary rate (n-1)/n convolutional codes is investigated. It is shown that for backward decoding based on the trellis of a syndrome former HT, the syndrome sequence must be generated in time-reversed order using an extra syndrome former H*T, where H* is a generator matrix of the reciprocal dual code of the original code. It is also shown that if the syndrome bits are generated once and only once using HT and H*T, then the corresponding two error sequences have the intersection of n error symbols, where is the memory length of HT.

Digital signal processors (DSPs) usually employ indirect addressing using an address register (AR) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. In this paper, AR update scheme is extended such that address can be efficiently modified by 2 in addition to conventional 1 updates. An automatic address allocation method of program variables for this new addressing model is presented. The method formulates program variables and AR modifications by a graph, and extracts a maximum chained triangle graph, which is accessed only by AR 1 and 2 operations, so that the estimated number of overhead codes is minimized. The proposed methods are applied to a DSP compiler, and memory allocations derived for several examples are compared with memory allocations by other methods.

In this paper, we propose a new multicast address scheme based on bit map address (BA) and vertex isolation address (VIA) schemes. The proposed scheme can be utilized by the self-routing switch in a speed manner, while preserving the multicast capability. We analyze the processing delay of the proposed scheme and show the efficiency.

The address-based queues are widely used in shared buffer ATM switches to guarantee the order of the cell delivery. In this paper, we propose an address-based queue mechanism to achieve an efficient use of the shared memory under a multicast service. In the switch, both cells and the address queues share the common memory. Each queue length changes flexibly according to the number of the stored cells. Our approach significantly reduces the cell loss probability as compared with the previously proposed approaches.

A simple method of compensating the DC drift of LiNbO3 Mach-Zehnder intensity modulators for very high speed optical transmission systems is proposed. This method adds low frequency perturbation to the modulator driving signal, and controls the bias voltage using the detected envelope of the modulator output signal. The control circuit is successfully demonstrated to work with less than a 0. 1-dB power penalty.

A method is proposed for estimating the error of whole-body average specific absorption rate (SAR) of an infinite-length cylindrical model of man exposed to TM microwave. At high frequencies, the average SAR of the infinite-length cylindrical model is approximately 5% smaller than that of the finite-length cylindrical model.

Fast and low-power circuit techniques suitable for size-configurable SRAM macrocells are described. An SRAM cell architecture using virtual-GND lines along bitlines is proposed; each virtual-GND line switches the potential by inner read-enable and column-address-decoded signals. Reducing the active power dissipation in the memory array and shortening the time for writing data are simultaneously accomplished. The range of available supply voltages is enhanced by adoptive higher virtual-GND level control with a simple voltage limiter. An SRAM-macrocell test chip is designed and fabricated with 0.5-µm CMOS technology. A 4K-word6-bit organization SRAM demonstrates 186-MHz operation at a 3.3-V typical power supply. Its power dissipation at a practical operating frequency, 100-MHz, is reduced to 29% (25-mW) by the proposed virtual-GND line techniques.

Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

Gaussian beams constitute a very powerful tool to analyze radiation and scattering problems in high frequency regimes. The analysis of this kind of beams may be done by performing an analytical continuation of the real sources into the complex space. This is also a very powerful technique that arise, not only to this kind of solutions, but also to other solutions that may be very useful even for low frequency regimes. A complete parametrization of real propagation space in terms of the different type of complex beams solutions is presented in this paper. The analysis in the complex domain arises to different regions in the real space which may be anticipated and described through analytical transition regions. Some important conclusions may be derived from the results obtained, in particular the results related to the complex far field condition.

In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

In this paper, we first prove that the Randomly Addressed Polling (RAP) protocol is unstable under the random access channel with heavy traffic. We also show that network stability can be ensured by controlling the arrival rate λ or by expanding the available addresses p on the assumption that there are M finite stations within the coverage of the controller (the base station). From analyses and results, we see the equilibrium of arrival rate is inversely proportional to the product of users (stations) and the exponent of stations. We also see that the maximum throughput can be derived at the point of λ1/M. This maximum performance can be easily obtained under the consideration of RAP protocol's stability. It also implies that the maximum throughput is independent of the available addresses of RAP protocol when pM.

Small-scale video on demand system will be necessary in the future. Cluster drives, which use optical disk drives, are a good buffer memory for this purpose because the cost per megabyte is low. An ordinary optical cluster drive has many SCSI buses and up to seven optical drives are connected to each SCSI bus. One drive from each bus is assembled to make a group of a cluster drive. The difference betweeen SCSI bus data transfer rate and sustained disk transfer rate enables the cluster drive to be simplified. Several drives on an SCSI bus make a sub-group. The video data is striped onto those sub-groups. When the total data transfer rate from disks within a sub-group exceeds the bus transfer rate, some drives can not acquire the bus. When drives connected to one SCSI bus are not identical, the block size of the data to be recorded on each drive has to be adjusted so that the maximum effective data transfer rate can be obtained. When the cycle times of a slow and fast drive are set identical, the effective data transfer rate is maximum, where one cycle consists of command time, minimum bus free time, disk read time, and bus transfer time.

A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.

In this paper,a protocol-based modeling and simulation method of performance evaluation for heavy traffic and transient LAN is proposed. In the method a node on a LAN is modeled as a set of detailed communication protocol models. By parallel and event driven processing of the models, high accuracy and high time-resolution of evaluation of LAN behaviors can be obtained at multi-layer protocols. The LANs at computer education sites have highly loaded peaks, and it is very hard to design large scale educational LANs. Proposed method can be used to evaluate such cases of heavy traffic and transient LAN.

An extension is made for a set of systems that have a quadratic Lyapunov function in common for the purpose of analysis and design. The nominal set of system matrices comprises stable symmetric matricies, which admit a hyperspherical Lyapunov function. Based on stability robustness results, sets of matrices are constructed so that they share the same Lyapunov function with the nominal ones.