Backfire quadrifilar helical antennas combined with parasitic loops are investigated in detail, focusing on clarifying the function of parasitic loops. First, the basic property is examined for the case of one parasitic loop, and it is found that the loop behaves as a director when the circumferential length of the loop is nearly 0. 9λ, and a reflector when the circumferential length of the loop is nearly 1. 2λ provided the distance between the parasitic loop and the top plane of helical antennas is approximately 0. 1λ, where λ is the wavelength. Next, the function of the parasitic loop is investigated by comparing the current distributions on the helices and the loop with those on a monofilar helix with a ground plane. It is found that the function of the parasitic loop is quite different from that of the ground plane. Then, the case of two parasitic loops is examined, and it is shown that the use of two parasitic loops is very effective and simple measures to control the radiation pattern and gain of the backfire quadrifilar helical antennas. Finally, for this type of antennas with two parasitic loops, an example of structural parameters suited to the use in satellite communications is presented.

We have analyzed a displayed image of TFT-LCD three-dimensionally in case of low power drive using Multi-Field Driving Method (MFD). We have also proposed a concept of multi-media driving method using MFD in which a displayed image was divided into some interlaced subfield images and the number of interlaced subfields can be changed depending on the moving quantities of displayed images. This method made it possible not only to reduce a driving power consumption in case of still images to less than half, compared to that with conventional methods, but also to maintain high moving image quality.

We propose and demonstrate a simple polarization-independent construction of a local node for optical WDM ring networks using a centralized multiwavelength light source (MWLS). The node is simply composed of a 4-port optical circulator, an add/drop multiplexing (ADM) filter, a reflective modulator, and a drop fiber Bragg grating (FBG). A Faraday rotator mirror (FRM) is used to enable an LiNbO3 intensity modulator to operate in the polarization-independent mode. We examine three ADM filters, an interference filter, a fiber Fabry-Perot (FP) filter, and a set of FBG's. An optical WDM system experiment is performed to demonstrate the feasibility of the proposed node construction.

In order to lessen overflow or underflow problem in numerical computation, several new floating-point arithmetics have been proposed. The significant advantage of these new arithmetics is that a number can be represented in a wider range since the fields of exponent and mantissa are changed depending on the magnitude of number. The main issues of these arithmetics are how to find the boundary between exponent and mantissa as well as to convert the formats between new floating-point arithmetic and fixed-point arithmetic quickly. In this paper, a CAM-based array converter based on the Universal Representation of Real number (URR) floating-point arithmetic is described. Using match retrieval device CAM, the detection of the boundary can be accomplished faster than conventional circuits. Arranging the basic cells into iterative array structure, the fast separation/connection operation is achieved. The speed, area and power consumption of the converter is estimated.

Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including cache memory, we can exploit such high on-chip memory bandwidth by means of replacing a whole cache line (or cache block) at a time on cache misses. This approach tends to increase the cache-line size if we attempt to improve the attainable memory bandwidth. Larger cache lines, however, might worsen the system performance if programs running on the LSIs do not have enough spatial locality of references and cache misses frequently take place. This paper describes a novel cache architecture suitable for merged DRAM/logic LSIs, called variable line-size cache or VLS cache, for resolving the above-mentioned dilemma. The VLS cache can make good use of the high on-chip memory bandwidth by means of larger cache lines and, at the same time, alleviate the negative effects of larger cache-line size by partitioning each large cache line into multiple sub-lines and allowing every sub-line to work as an independent cache line. The number of sub-lines involved when a cache replacement occurs can be determined depending on the characteristics of programs. This paper also evaluates the cost/performance improvements attainable by the VLS cache and compares it with those of conventional cache architectures. As a result, it is observed that a VLS cache reduces the average memory-access time by 16. 4% while it increases the hardware cost by only 13%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. In order to reconsider the DRAM data retention characteristics, this paper formulates and evaluates the performance degradation due to conflicts between normal DRAM accesses and refresh operations. Next, this paper proposes a new DRAM refresh architecture which intends to reduce unnecessary refreshes. This architecture exploits multiple refresh periods. Each row is refreshed with the most appropriate period of them. Reducing the number of refreshes improves the accessibility to DRAM. It is shown that the method reduces the number of refreshes and the degree of the performance degradation of the logic portion.

In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.

This paper describes the analysis of the Stacked-Surrounding Gate Transistor (S-SGT) DRAM for the high speed and low voltage operation. The S-SGT DRAM is based on the new three dimensional (3D)-building memory array technology. In terms of the bit-lines signal voltage for read operation, it is found that the signal voltage of the S-SGT DRAM is larger than that of the conventional planar DRAM, the NAND-structured DRAM, and the SGT DRAM. The signal voltage of the S-SGT DRAM was found to depend on the pillar radius, the distance between the bit-line and the substrate, and the number of cells connected to one bit-line in comparison with the above three kinds of conventional DRAMs. Especially, with reducing the pillar radius (R), the signal voltage of the S-SGT DRAM becomes larger. In the concrete, in case that R is 0. 25 µm, the signal voltage of the S-SGT DRAM is about 160%, 160% and 120% in comparison with the planar DRAM, the SGT DRAM and the NAND-structured DRAM, respectively. Therefore, the S-SGT DRAM can realize larger S/N ratio. This advantage can realize the high speed and low voltage operation. Moreover, in case that the signal voltage is constant (0.15 V), the maximum number of cells connected to one bit-line for the S-SGT DRAM is about 2 times in comparison with the planar DRAM. This advantage makes it possible to reduce the number of both sense amplifiers and bit-lines. This is very suitable for reducing the total chip size of the S-SGT DRAM. Above all, it was found that the S-SGT DRAM is one of candidates for the high speed and low voltage operation DRAM in the future.

Planar lightwave circuits (PLCs) provide various important devices for optical wavelength division multiplexing (WDM) systems, subscriber networks and etc. This paper reviews the recent progress and future prospects of PLC technologies including arrayed-waveguide grating multiplexers, optical add/drop multiplexers, programmable dispersion equalizers and hybrid optoelectronics integration technologies.

High- and low-reflection Bragg gratings with a flat-top spectral response free from ripples are proposed. Add/drop filters are created based on gratings photoinduced on planar waveguides by using the new design schemes. The measured spectral responses for the high and low reflection gratings are in good agreement with the calculated ones, and show the flat-top spectral responses.

The new technique for reducing the load latency is presented. This technique, named tunneling-load, utilizes the register specifier buffer in order to reduce the load latency without fetching the data cache speculatively, and thus eliminates the drawback of any load address prediction techniques. As a consequence of the trend toward increasing clock frequency, the internal cache is no longer able to fill the speed gap between the processor and the external memory, and the data cache latency degrades the processor performance. In order to hide this latency, several techniques predicting the load address have been proposed. These techniques carry out the speculative data cache fetching, which causes the explosion of the memory traffic and the pollution of the data cache. The tunneling-load solves these problems. We have evaluated the effects of the tunneling-load, and found that in an in-order-issue superscalar platform the instruction level parallelism is increased by approximately 10%.

A combined mode-matching and moment method is proposed to calculate the capacitance matrix of wedge-supported cylindrical microstrip lines with an indented ground. Each indent is modeled as a multilayered medium in which the potential distribution is systematically derived by defining reflection matrices. An integral equation is derived in terms of the charge distribution on the strip surfaces. Galerkin's method is then applied to solve the integral equation for the charge distribution. The effects of strip width, strip separation, indent depth, and indent shape are analyzed.

Two new algorithms are introduced, respectively called syndrome erasing and double syndrome decoding, which permit to achieve fast error correction with a wide class of cyclic codes.

In order to improve the running durability of organic electroluminescent devices (OELDs), the doping sites of molecular OELDs were optimized, and the frequency responses of the optimized devices were examined for Mg-In/bis (10-hydroxybenzo[h]quinolinate) beryllium (BeBq2)/N, N'-diphenyl-N, N'-(3-methylphenyl)-1, 1'-biphenyl-4, 4'-diamine (TPD)/4, 4', 4"-tris (3-methylphenylphenylamino) triphenylamine (MTDATA)/ITO. The TPD hole transport layer was the optimum doping site for 5, 6, 11, 12-tetraphenylnaphthacene (rubrene) dopant, and a very high efficiency of 13 cd/A at 0. 13 kcd/m2 was obtained for yellow emission. Half-decay times under a constant direct current density of 1. 0 mA/cm2 from an initial luminance of 0. 13 kcd/m2 extended to longer than 26,000 hours. The luminance of the optimized device decreases lineally with respect to the logarithm of the frequency as the frequency increases in the range from 1 kHz to 0. 3 MHz when a square wave with a duty ratio of 50% and a maximum voltage of 5.0 V is applied. A new driving method involving frequency modulation is proposed. This may offer accurate control of pixel luminance, and enable simple driving circuits adapted to highly integrated digital LSI chips, or the concept of system on glass.

This paper proposes the Dual Zipfian Model addressing how to describe HTTP access trends in large-scale data communication networks, and discusses how to design the capacity of address cache tables in an edge router of the networks. We show that destination addresses of packets can be characterized by two types of Zipf's law. Fundamental concept of the Dual Zipfian Model is in complementary use of these laws, and we can derive the relationship between the number of accesses and the number of destination addresses. Experimental results show that the relation gives a good approximation. Applying this relation, we derive cache hit probabilities of the address cache table that incorporates high-speed address resolution. Using the probabilities, design issues including the capacity of the cache tables and aging algorithms of cache entries are also discussed.

We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.

In a secure partially blind signature scheme, the signer assures that the blind signatures issued by him contains the information he desires. The techniques make it possible to minimize the unlimited growth of the bank's database which storing all spent electronic cash in an anonymous electronic cash system. In this paper we propose an efficient partially blind signature scheme for electronic cash. In our scheme, only several modular additions and modular multiplications are required for a signature requester to obtain and verify a signature. It turns out that the proposed scheme is suitable for mobile clients and smart-card applications because no time-consuming computations are required, such as modular exponentiation and inverse computations. Comparing with the existing blind signature schemes proposed in the literatures, our method reduces the amount of computations for signature requesters by almost 98%.

Multi-recast techniques make it possible for a voter to participate in a sequence of different designated votings by using only one ticket. In a multi-recastable ticket scheme for electronic voting, every voter of a group can obtain an m-castable ticket (m-ticket), and through the m-ticket, the voter can participate in a sequence of m different designated votings held in this group. The m-ticket contains all possible intentions of the voter in the sequence of votings, and in each of the m votings, a voter casts his vote by just making appropriate modifications to his m-ticket. The authority cannot produce both the opposite version of a vote cast by a voter in one voting and the succeeding uncast votes of the voter. Only one round of registration action is required for a voter to request an m-ticket from the authority. Moreover, the size of such an m-ticket is not larger than that of an ordinary vote. It turns out that the proposed scheme greatly reduces the network traffic between the voters and the authority during the registration stages in a sequence of different votings, for example, the proposed method reduces the communication traffic by almost 80% for a sequence of 5 votings and by nearly 90% for a sequence of 10 votings.

The features for the integration of 1Tr/1C DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.

We prepared alkoxide solutions to fabricate SrBi2Ta2O9 (SBT) ferroelectric capacitors with IrO2 electrodes. In this process, to minimize excess bismuth, the Sr : Bi : Ta mole ratio was kept at 0. 9 : 2. 1 : 2. 0, i. e. , nearly stoichiometric. Three types of solution - mixed-only (MIX), complexed (COMP), and hydrolyzed (HYD) - were used. The HYD capacitor had low absolute leakage current, 10-7 A/cm2 order, and good saturation properties to 6 V. When voltage was applied to each capacitor at 2 to 6 V, MIX and COMP capacitors showed only partial hysteresis loops due to a high leakage current, reflecting the I-V characteristics. These results are probably due to film density caused by metaloxane network bonding. A fatigue endurance test was conducted using cycling of polarization switching at 6 V using the HYD capacitor with IrO2 electrodes. Slight changes were, however, observed in hysteresis loop configuration, but good hysteresis properties were kept up to 1. 04 1012 cycles. We compared SBT ferroelectric thin films fabricated with Pt electrodes and with IrO2 electrodes. Scarcely any difference due to SBT in the XRD pattern was seen, depending on the substrate material. We found that the use of IrO2 electrodes had the effect of decreasing the crystallization temperature. On Pt and IrO2 electrodes, the two films have surface morphology quite different from that of the rod-like structure wellknown for SBT films prepared using a metal 2-ethylhexanate solution. Their surfaces show a similar morphology with relatively large, closely packed grains. A comparison of the I-V characteristics after reannealing showed that the capacitor with IrO2 electrodes had a higher leakage current than that with Pt electrodes. The leakage current was probably due to the density of the film and interface between the SBT film and electrodes.