A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

This paper proposes a compact, low-power, and rail-to-rail class-B output buffer for driving the large column line capacitance of LCDs. The comparator used as a nonlinear element in feedback path is modified from the current-mirror amplifier, which has area and power advantages. The output buffer was realized in a 0.35 m CMOS process. The active area of the buffer is 8673.5 m2. With a 3.3 V supply, the measured quiescent current is 7.4 A. The settling time for 0.05-3.25 V swing to within 0.2% is 8 s.

A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.

The surface film of a slip ring is important for the sliding contact phenomenon. The surface film is affected by atmospheric temperature, humidity and air pressure. The main objective of our study is to examine the effect of oxygen gas on the sliding contact phenomenon. In the present experiment, we examined the contact voltage drop for continuous sliding when the atmosphere is changed from low pressure to atmospheric pressure by introducing oxygen (O2 20%+N2 80%) or nitrogen gas. As a result, the contact voltage drop increases rapidly with increasing gas pressure, and its fluctuation also becomes large. These phenomena are observed in both cases of oxygen (O2 20%+N2 80%) and nitrogen introduction. The results clearly show that the sudden increase of contact voltage drop is affected by factors other than the oxide film. Actually, the oxide film is not formed in the nitrogen atmosphere. Furthermore, the frictional coefficient of carbon and copper ring is changed at ambient atmosphere. It is inferred from these data that the contact voltage drop may be affected by the frictional coefficient. When the gas pressure decreases again, the contact voltage drop does not suffer from the effect of ambient gas. Therefore, only the resistance of the oxide film appears to affect contact voltage drop. In this paper, the effect of sliding contact phenomenon on the contact voltage drop by gas adsorption and film generation was examined.

In this paper, a novel method of clock feedthrough reduction in CMOS autozeroed operational amplifiers with three-phase clock operation is presented. The operational amplifiers in the method are configured by two autozeroed-gain stages. The differential input stage and the second output gain stage are autozeroed individually by a three-phase clock for autozeroing. The three-phase clock is provided so as to finish the compensation period of the input stage earlier than the end of the second stage compensation period. This operation makes it possible to absorb affection of clock feedthrough in the input stage with the second stage. As a result, residual error of offset compensation is much reduced by the voltage gain of the first stage. The effect of the two-stage autozeroing has been confirmed with SPICE simulation and fabricated CMOS circuit. The results of SPICE simulation showed that the two-stage autozeroed operational amplifier has significant advantage as compared to conventional configuration. Affection of clock feedthrough is reduced to about 1/50 in the two-stage configuration. Fabricated CMOS circuit also showed high potential of the two-stage autozeroed operational amplifier for feedthrough reduction. It has been proven experimentally that the two-stage autozeroing is an effective design approach to reduce clock feedthrough error in CMOS autozeroed operational amplifiers.

To understand the characteristics of a multimedia service, such as the large volume of data transfer and real-time constraints, it is necessary to have a performance evaluation tool for an HDD. Our HDD simulator is running on a PC operated on FreeBSD UNIX OS. We first investigate the seek time and the sustained rate of HDDs and then evaluate the performance of an HDD for an experimental VOD system. Applying the experimental results, we find the bottleneck of an HDD, and then suggest what HDDs are to be selected for a VOD system.

A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.

We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.

We report on the analysis and fabrication of vertical PtSi Schottky source/drain metal oxide semiconductor field effect transistors (MOSFETs), which are suitable for combination with quantum effect devices such as resonant tunneling diodes. Analysis was carried out by one-dimensional approximation of the device structure, WKB approximation of the tunneling probability in Schottky barrier tunneling and self-consistent calculation. Theoretical calculation showed good drivability (750 µA/µm) of this device with tOX = 1 nm and tSi = 5 nm. As a preliminary experiment, devices with a Si channel thickness of 8 nm, 20 nm or 30 nm and a vertical channel length of 55 nm were fabricated. Although the drain current at the "on" state was small due to the thick gate oxide of 8 nm, analysis and measurement showed reasonable agreement with respect to the drivability. Based on the results of theoretical analysis, the device drivability can be much improved by reducing the gate oxide thickness.

In this paper, we consider a network design problem with hub-and-spoke structure. We propose a relaxation technique for the problem where the location of hub nodes is given and decides the allocation of non-hub nodes to one of the hub nodes. We linearize the non-convex quadratic objective function of the original problem, introducing Hitchcock transportation problems defined for each pair of non-hub nodes. We provide two linear relaxation problems, one based on the Hitchcock transportation problems and the other on the dual Hitchcock transportation problems. We show the tightness of the lower bounds obtained by our formulations by computational experiences.

This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.

A practical method of measuring the contact resistance of a phosphorus-doped poly-Si plug formed on a lightly phosphorus-doped diffusion region in DRAM memory cells is described. Contact resistance was obtained electrically, using ordinary contact-chain test structures, by changing the measurement of the substrate bias. This separated the bias-dependent resistance of the lightly doped diffusion layer from the total resistance. The method was used experimentally to evaluate the feasibility of forming low-resistance contacts down to a diameter of 130 nm for giga-bit DRAMs. Electrical measurement showed that reducing the interface resistance between the poly-Si plug and the lightly doped diffusion layer was effective for forming low-resistance contacts, though a specific interface layer could not be detected by TEM observation.

In 1998, Fan and Lei proposed a partially blind signature scheme that could reduce the computation load and the size of the database for electronic cash systems. In this Letter, we show that their scheme could not meet the untraceability property of a blind signature.

The main objective of vehicle suspensions is to improve ride comfort and road holding ability. Though passive suspensions consist of spring and damper, active suspensions adopt an actuator in addition to passive suspensions. In this paper, a quarter car model with an asymmetric hydraulic actuator is used. Moreover, the damping coefficient of the damper, which is changed according to the actuator velocity, is considered. The LPV (Linear Parameter Varying) model is obtained by applying feedback linearization technique. Next, a gain-scheduled controller, based on LQ regulator with different weighting factor, is designed according to the actuator velocity and the stability of the proposed controller is also proved. The effectiveness of the proposed controller is shown by numerical simulations.

Low cost optical subscriber systems and effective operation are indispensable to the construction and maintenance of greatly expanded optical fiber networks. An optical fiber line monitoring system is essential for reducing maintenance costs and improving service reliability in optical access networks. To promote cost-effective optical fiber line operation, we propose an extended automatic optical fiber operations support system (AURORA) with a remotely installed fiber selector. We suggest a configuration for extended AURORA and design the dynamic range of the system. We confirmed that testing could be carried out on an extended optical network section of 10 km in length by using extended AURORA when the optical trunk line was less than 15 km. We also discuss the effect on the maintenance cost of optical fiber cables in access networks. We calculated the annual maintenance cost for periodic tests in actual operation areas, and confirmed that this cost could be reduced by 30% compared with that for a conventional system.

As a center of mobile multimedia of the 21st century, it is very much looking forward to explosion of R&D and business of the next generation of mobile communication systems and the ITS (Intelligent Transport Systems) because ITS will enable information-oriented in the field of the road, traffic and vehicles, by using the most advanced technologies of mobile communications and devices, for the various purposes such as decrease of the traffic accident, the reduction of traffic jam, the increase in efficiency of the logistics and the harmony with the earth environment. This invited paper will first briefly introduce evolution of mobile communications and ITS in ministries, industries and academia in Japan. Then core communication technologies for ITS will be overviewed such as spread spectrum CDMA, adaptive antenna array, and software radio or software defined radio. Demands of SoC (System on a Chip) to carry out the core technologies will be addressed.

In this paper, we propose a probabilistic approach to derive an approximate polyhedral description from range data. We first compare several least-squares-based methods for estimation of local normal vectors and select the most robust one based on a reasonable noise model of the range data. Second, we extract the stable planar regions from the range data by examining the distributions of the local normal vectors together with their spatial information in the 2D range image. Instead of segmenting the range data completely, we use only the geometries of the extracted stable planar regions to derive a polyhedral description of the range data. The curved surfaces in the range data are approximated by their extracted plane patches. With a probabilistic approach, the proposed method can be expected to be robust against the noise. Experimental results on real range data from different sources show the effectiveness of the proposed method.

An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4-GHz and 5.2-GHz short-range wireless applications. The ICs are fabricated in a 0.18 µm bulk CMOS which has no extra processing steps for enhancing the RF performance. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in the bulk CMOS leading to large RF substrate and conductor losses. The main measurement results of the two LN/D-As are as follows: a 3.8-dB noise figure (NF) and a 10.1-dB gain under the conditions of 1.8 V and 6 mA, a 3.4-dBm 1-dB gain compressed output power (P1dB) for a 2.4-V voltage supply and a 13-mA operating current for the 2.4-GHz LN/D-A, and a 4.9-dB NF and an 11.1-dB gain with a 1.8 V and 10 mA supply condition, a 2.3-dBm P1dB at 2.4 V and 16 mA for the 5.2-GHz LN/D-A. Both MMICs are suited for low-noise amplifiers and driver amplifiers in 2.4-GHz and 5.2-GHz low-cost, low-power wireless systems such as Bluetooth and hiperLAN.

In recent years, several inverse solutions of magnetoencephalography (MEG) have been proposed. Among them, the multiple signal classification (MUSIC) method utilizes spatio-temporal information obtained from magnetic fields. The conventional MUSIC method is, however, sensitive to Gaussian noise and a sufficiently large signal-to-noise ratio (SNR) is required to estimate the number of sources and to specify the precise locations of electrical neural activities. In this paper, a new algorithm for solving the inverse problem using the fourth order MUSIC (FO-MUSIC) method is proposed. We apply it to the MEG source estimation problem. Numerical simulations demonstrate that the proposed FO-MUSIC algorithm is more robust against Gaussian noise than the conventional MUSIC algorithm.