This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

We propose an interactive identification scheme based on the quadratic residue problem. Prover's identity can be proved without revealing his secret information with only one accreditation. The proposed scheme requires few computations in the verification process, and a small amount of memory to store the secret information, A digital signature based on this scheme is proposed, and its validity is then proved. Lastly, analysis about the proposed scheme is presented at the end of the paper.

A sparse memory access architecture which is proposed to achieve a high-computational-speed neural-network LSI is described in detail. This architecture uses two key techniques, compressible synapse-weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neuron calculations without incurring an accuracy penalty. The test chip based on this architecture has 96 parallel data-driven processing units and enough memory for 12,288 synapse weights. In a pattern recognition example, the number of memory accesses and neuron calculations was reduced to 0.87% that needed in the conventional method and the practical performance was 18 GCPS. The sparse memory access architecture is also effective when the synapse weights are stored in off-chip memory.

This paper describes the effectiveness of stream-oriented data-driven scheme for achieving autonomous fault management of hyper-distributed systems such as networks based on the Telecommunications Information Networking Architecture (TINA). TINA, whose specifications are in the finalizing phase within TINA-Consortium, is aiming at achieving interoperability and reusability of telecom applications software and independent of underlying technologies. However, to actually implement TINA network, it is essential to consider the technology constraints. Especially autonomous fault management at run-time is crucial for distributed network environment because centralized control using global information is very difficult. So far many works have been done on so-called off-line management but runtime management of service failure seems immature. This paper proposes introduction of stream-oriented data-driven processors to the autonomous fault management at runtime in TINA based distributed network environment. It examines the features of distributed network applications and technology requirements to achieve fault management of those distributed applications such as effective multiprocessing of surveillance, testing, reconfiguration in addition to ordinary processing.

A noble blind equalization algorithm (BEA) using a single/multilevel modulus is proposed. According to the residual intersymbol interference (ISI) level of the equalizer output, the new algorithm adopts relevantly a single modulus or a multilevel modulus to form its cost function. Moreover, since the proposed approach separates complex two-dimensional signal into in-phase and quadrature components, and forms the error signals for each component, it has inherently the capability of phase recovery. Hence, it improves the performances of steady-state and recovers the phase rotation without any degradation of transient property. Simulation results confirm the effectiveness of the new approach.

This paper describes a neuro-based optimization algorithm for three dimensional (3-D) cylindric puzzles which are problems to arrange the irregular-shaped slices so that they perfectly fit into a fixed three dimensional cylindric shape. First, the idea to expand the 2-dimensional tiling technique to 3-dimensional puzzles is described. Next, to energy function with the fitting function of each polyomino is introduced, which is available for 3-D cylindric puzzles. Furthermore our algorithm is applied to several examples using the analog neural array. Finally, it is shown that our algorithm is useful for solving 3-D cylindric puzzles.

Modern database systems have to support complex data objects, which appear in advanced data models such as object-oriented data models and nested relational data models. Set-valued objects are basic constructs to build complex structures in those models. Therefore, efficient processing of set-valued object retrieval (simply, set retrieval) is an important feature required of advanced database systems. Our previous work proposed a basic scheme to apply superimposed coded signature files to set retrieval and showed its potential advantages over the B-tree index based approach using a performance analysis model. Retrieval with signature files is always accompanied by mismatches called false drops, and proper control of the false drops is indispensable in the signature file design. This study intensively analyzes the false drops in set retrieval with signature files. First, schemes to use signature files are presented to process set retrieval involving "has-subset," "is-subset," "has-intersection," and "is-equal" predicates, and generic formulas estimating the false drops are derived. Then, three sets of concrete formulas are derived in three ways to estimate the false drops in the four types of set retrieval. Finally, their estimates are validated with computer simulations, and advantages and disadvantages of each set of the false drop estimation formulas are discussed. The analysis shows that proper choice of estimation formulas gives quite accurate estimates of the false drops in set retrieval with signature files.

We extend the Rabin cryptosystem to the Eisenstein and Gauss fields. Methods for constructing the complete representation class and modulo operation of the ideal are presented. Based on these, we describe the methods of encryption and decryption. This proposed cryptosystem is shown to be as intractable as factorization, and recently presented low exponent attacks do not work against it.

The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

This paper proposes a new test mode circuit which enables the massively parallel test of DRAMs with a standard LSI tester with little chip area penalty. It is useful to enhance the test throughput that can't be improved by the conventional multi-bit test mode. And a new redundancy circuit that detects and repairs the short circuit failures in the memory cell array is also proposed. It greatly improves the yield of super low power 256 Mbit DRAMs.

The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

A 2.7-V Si-bipolar quadrature modulator with a 90 phase shifter consisting of a frequency doubler and a master-slave flip-flop is described. The modulator operates over a wide bandwidth (0.95 to 1.88 GHz) without any tuning or adjustments. It is implemented using 20-GHz Si-bipolar technology and dissipates 97 mW at 2.7 V. An image ratio of less than -40 dBc is obtained between 1.1 and 1.8 GHz. Moreover, third-order harmonic products are less than -40 dBc and carrier leakage is less than -30 dBc.

High-end graphic systems with 3 million pixels require 8-bit D/A converters with more than 300-MS/s conversion rate. Furthermore, D/A converters need to operate with low supply voltage when they are integrated with large-scale digital circuits on a harf-micron CMOS process. This paper describes a 350-MS/s 8-bit CMOS D/A converter with 3.3-V power supply. A current source circuit with a delayed driving scheme is developed. This driving scheme reduces a fluctuation of internal node voltage of the current source circuit and high-speed swiching is realized. In addition to this driving scheme, two stages of latches are inserted into matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-µm CMOS process with single poly-silicon layer and double aluminum layers. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s.

Hankel's asymptotic expansions are frequently used for numerical calculation of cylindrical functions of complex order. We beforehand need to estimate the precisions of the cylindrical functions calculated with Hankel's asymptotic expansions in order to use these expansions. This letter presents comparatively simple expressions for rough estimations of the errors of the cylindrical functions calculated with the asymptotic expansions, and features of the errors are discussed.

This paper describes a novel quasi-transmission-line variable-reactance circuit that extends the variable-phase range of phase shifters. It consists of a transmission line and two shunt varactors. By appropriately choosing the characteristic impedance and electrical length of the transmission line, the variable-phase range can be significantly increased. Since the proposed circuit can be fabricated by the conventional MESFET process, a phase shifter can be integrated with other functional circuits. This enables fully monolithic integration of RF circuits as a one-chip multi-functional MMIC in radio communication systems. The variable-phase range of the prototype X-band monolithic phase shifter is 208 degrees, which is approximately four times as large as that of conventional one.

So far, neuronal dendrites have been characterized as electrically passive cables. However, recent physiological findings have revealed complex dynamics due to active conductances distributed over dendrites. In particular, the voltage-gated calcium and calcium-activated conductances are essential for producing diverse neuronal dynamics and synaptic plasticity. In this paper, we investigate the functional significance of the dendritic calcium-activated dynamics by computer simulations. First, the dendritic calcium-activated responses are modeled in a discrete compartmental form based on the physiological findings. Second, the basic stimulus-response characteristics of the single compartment dendrite model are investigated. The model is shown to reproduce the neuronal responses qualitatively. Third, the spatio-temporal dynamics of the dendrite shafts are modeled by longitudinally connecting 10 single compartments with coupling constants which are responsible for the dendrite thickness. The thick dendrite models, corresponding to proximal dendrites, respond in a spatially cooperative manner to a localized constant or periodic current stimulation. In contrast, the highly activated compartments are forced to be localized in the neighborhood of the stimulation-site in the fine dendrite models corresponding to distal dendrites. These results suggest that dendritic activities are spatially cooperated in a site-dependent manner.

This paper presents the performance of a proposed GaAs MESFET photodetector with wide drain-to-gate distances for improving the optical coupling efficiency in subcarrier optical transmission. Principle and design parameters of the proposed MESFET are described. Link gain, CNR, and BER, are experimentally investigated as functions of the drain-to-gate distance. It is experimentally found that the proposed MESFET improves the link gain by 8.5 dB compared to the conventional structure at the subcarrier frequency of 140 MHz. Discussions are also included compared to PIN-PD.