This paper deals with a method for designing the driving circuit of an electroluminescent (EL) element whose power consumption is lower and the deviation of output voltage is smaller even when the EL element is replaced with another of a different shape. In this driving circuit, an AC voltage raised by a step-up transformer is supplied to the EL element. The oscillation conditions in the orthodox driving circuits were theoretically analyzed, and a new driving circuit which incorporates these characteristics is proposed. A new prototype driving circuit taking the resonance characteristics between the capacitance of the element and the inductance of the transformer into consideration was made. In the experiment, an inorganic AC EL cable-type element was used as the load of the driving circuit as its impedance can be easily adjusted by changing its length. In comparison with orthodox circuits, the power consumption was lower and the changes in the output voltage were smaller in the new prototype circuit even when the changes in the impedance were large.

Randomly addressed polling was proposed as a multiple access control protocol for wireless local area networks (LANs). However, the protocol has difficulties in supporting real-time services such as voice transmission. We propose a reservation scheme and make it possible to support real-time services. The scheme is described in detail. Efficiency and average access delay are analyzed.

This paper proposes and investigates a coding and decoding scheme to achieve adaptive channel coding using a Finite State Machine (FSM) for Software Defined Radio (SDR). Adaptive channel coding and decoding systems that can switch between different coding rates and error correcting capabilities in order to adapt to changing applications and environments, are effective for SDR. However, in these systems, a receiver cannot always select the correct decoder which causes decoding errors, usually referred to as Decoder-Selection-Errors (DSE). We propose a trellis encoder estimation scheme that compensates for this problem. This scheme uses the circuit of FSM to limit the encoder transition and the Viterbi algorithm for maximum likelihood trellis encoder estimation. Computer simulations are applied for evaluating the DSE rate, the Bit Error Rate (BER) and Throughput of the proposed scheme in comparison with a conventional scheme.

In this paper, we focus attention on the development of security techniques using software defined radio (SDR) technologies. We propose a new secure download system which uses the characteristics of the field programmable gate arrays (FPGAs) composing the SDR. The proposed system has the novelty that realization of high security encipherment is possible. This is achieved using the characteristic of FPGAs which allows systems to be arranged in a variety of different layouts, as well as by using the configuration information as the key. This unifies the renewal of the key and the encipherment. In addition the proposed system has the merit that it has high security against illegal acquisition such as a wiretapping, and can also be used in conjunction with any other current cipher algorithm. As an evaluation of the security, we show that the proposed system has high immunity to illegal acquisition of software using replay attack, by verification of the protocol as well as by numerical computation. The proposed system can therefore realize high security software downloads based on SDR.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

This paper presents an adaptive burst-mode M-QAM modem architecture suitable for variable rate broadband wireless packet data networks. The core signal processing functions for the modem are common to all constellations resulting in an efficient hardware architecture for field programmable gate array (FPGA) implementation.

Software Defined Radio is beyond the education and initiation phase. The industry is addressing the needs of reconfigurable radio technology development, implementation, and application in a variety of marketplaces. Regulatory decisions are being formulated to facilitate SDR adoption and deployment. Continued dialog and cooperation among the industry organizations is an important factor in the rate of progress.

Software radio promises to bring unparalleled flexibility and reconfigurability to wireless systems, with enormous commercial potential. As the next decade progresses SDR is expected by many to emerge as the dominant design in the commercial wireless marketplace. However, significant practical issues associated with security and regulation exist which, if not adequately addressed, could threaten to result in regulatory hurdles precluding, or at least delaying, its deployment--a regulator could be understandably hesitant about authorising the operation of a handset whose radio emissions can be determined by an end user downloading and using unproven software from an arbitrary source post-purchase. In this article we describe the Reconfiguration Management Architecture--a pragmatic technological approach, developed within the framework of Mobile VCE research, that offers solutions to this and other associated SDR problems. The RMA approach fully acknowledges and builds upon the necessary interaction between the user terminal and the network to allow full validation of a reconfigured user device prior to realtime operational authorisation. Such an architecture allows responsibility for validation to be delegated and assigned by a national regulator to, for example, a mobile network operator. Such a capability can, in turn, facilitate the creation and growth of an open market in downloadable software provision, which itself promises to encourage rapid development of new capabilities, applications and innovation. New business models and revenue streams may be expected to result. This article describes the basic technical concepts associated with the RMA, explaining the key functionalities residing within the terminal and the network and their interrelationships. The RMA is presently being evaluated as part of the SDR Forum's security and architecture work. It promises to provide realistic solutions that could accelerate the successful commercial deployment and rollout of SDR technology to the benefit of the industry, across the whole value chain.

To promote the commercial implementation of software download for software defined radio (SDR) terminals, a secure method of download is vital. This paper examines the needs of software download for SDR, and proposes a comprehensive system framework within which secure download can be carried out. The features of the proposed system include unique individual encryption to each terminal and secure exchangeability of any cryptographic components. The main goals of the security system are the following: (i) verification of the identity of the source of the software; (ii) control and verification of the integrity of the downloaded data; (iii) disabling of the ability to run unauthorized software on the software defined terminal; (iv) secrecy of the transmitted data. The proposed system is flexible and in harmony with current requirements regarding the SDR security issues.

A software defined radio (SDR) prototype based on a multiprocessor architecture (MPA) is developed. Software for Japanese personal handy phone system (PHS) of a 2G mobile system, and IEEE 802.11 wireless LAN, which has much wider bandwidth than the 2G systems, is successfully implemented. Newly developed flexible-rate pre-/ post-processor (FR-PPP) achieves the flexibility and wideband performance that the platform needs. This paper shows the design of the SDR prototype and evaluates its performance by experiments that include PHS processor load and wireless LAN throughput characteristics and processor load.

A novel compact T/R (Transmit/Receive) switching circuit for wideband T/R modules has been proposed. It employs quadrature couplers and gate-and-drain-driven HPAs to remove circulators or T/R switches from a conventional T/R module, and T/R switching is made with controlling biasing conditions of the FETs in HPAs. Furthermore, an optimum biasing condition and design of output matching circuit of the HPA have been studied to reduce loss in RX-mode, and the validity of the method has been confirmed by measurements.

This paper proposes a new algorithm named WGF (Weight-Gap First) scheduling. It not only supports the maximum throughput of a cell, but also provides the fairness of a terminal in HDR. The WG-based new scheduling algorithm is determined by served data of mobile terminals to guarantee requested data rate. WGs are renewed at each timeslot to improve throughput and fairness. Simulations confirm the better performance of the proposed algorithm in terms of throughput and fairness.

This paper discusses a design methodology suitable for the development of software defined radio platforms. A flexible digital receiver was designed and implemented using a multi-port direct converter and an FPGA-based platform. The design starts with a hardware-oriented top-level system model. The model is built based on basic signal processing blocks connected together in a graphical tool. Carrier symbol timing recovery is implemented in the discrete-time (digital) domain with an interpolator-based synchronizer. Carrier phase and frequency are recovered using a feedback synchronization algorithm (a second-order type-II digital PLL). Experimental results of the platform and its simulation results demonstrate the effectiveness of the proposed design methodology.

A broadband RF front-end having a direct conversion architecture has been developed. The RF front-end consists of two broadband quadrature mixers, a multi-band local oscillator, and a broadband low-noise variable gain amplifier (LNVGA). The mixer achieves broadband characteristics through the incorporation of an in-phase power divider and a 45-degree power divider. The in-phase power divider achieves broadband characteristics through the addition of a compensation capacitor. The 45-degree power divider achieves broadband phase characteristics through the addition of a compensation capacitor and a compensation resistor. The local oscillator, which is composed of two VCOs, two frequency dividers, and four switches, can cover three systems including one FDD system. The LNVGA achieves its broadband characteristics without the use of reactance elements, such as inductors or capacitors. In a trial demonstration, when the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a demodulator experimentally demonstrated an amplitude balance of less than 1.6 dB and a quadrature phase error of less than 3 degrees. When the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a modulator demonstrated an image ratio of less than -30 dBc. The local oscillator demonstrated multi-band characteristics, which are able to cover the target frequencies for three systems (PDC, PHS, 2.4 GHz WLAN). From 900 MHz to 2.5 GHz, the amplifier shows a noise figure of less than 2.1 dB and a gain of 28 1.6 dB.

This paper presents a novel system-level design methodology, called quality-driven design, by which application-specific optimization can be achieved; furthermore the entire functionality can be shared to maximize design reuse. As a case of study, this paper focuses on quality-driven design for video applications and introduces an output quality adaptive approach based on variable bitwidth optimization to explore a new design space. MPEG2 video is used as the driver application to illustrate the potential of the presented methodology. Experimental results show the effectiveness of the methodology.

This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

We developed the new electron gun, which can emit about twice electron in comparison with the conventional gun and could achieve the screen brightness of over 300 cd/m2 even if the ordinal driving circuit is applied. We tried two methods to improve the drive characteristics, and we chose to lower the cathode cut-off voltage. To maintain the resolution, we optimized the triode. And we used the tungsten-coated oxide cathode to guarantee the long life.

This paper presents efficient file management of a hard disk drive embedded digital satellite receiver. The digital broadcasting technology enables multimedia access via broadcasting systems. The amount of digital data to be processed is increased remarkably as compared to the previous analog broadcasting environments. The efficient digital data storage and management technology are discussed in this paper to cope with these changes. The DSR uses a new file system that is designed by considering disk cluster sizes and limited memories in the system, which is more appropriate than that of general Personal Computers. The proposed system enables us to watch broadcasting and to manage multimedia data efficiently.

The fields in the junctions between straight and curved rectangular waveguides are analyzed by using the method of separating variables. This method was succeeded because the authors developed the method of numerical calculation of the cylindrical functions of complex order. As a result, we numerically calculate the reflection and transmission coefficients in the junctions in various situations, and we compare these results with the results by the perturbation method and with the results by Jui-Pang et al.

In this paper a new MOS charge pump architecture is presented, where a clock generator is used in each pump stage of the charge pump circuit to elevate voltage exponentially with stages. This charge pump with a clock level shifter is designed to run at an optimized operation frequency, which can make an excellent compromise between the rise time and the dynamic power dissipation. With less stages than the linear-cascade circuit, the power dissipation and the area of the novel charge pump circuit are markedly decreased. The simulating comparison results based on 1.2 µm CMOS, p-substrate double-poly double-metal process parameters show that the nonlinear charge pump with a high pumping efficiency can supply a steady 1 mA, 16 v output for portable LCDs.