By integrating three networks, namely, Public Switched Telephone Network (PSTN), Personal Handy-Phone System (PHS) and Intelligent Network (IN) to work together as a Personal Communication Telephone (PCT) service to be offered in the Bangkok metropolis area, the PCT service enables the advent of three new concepts, first, using the same telephone number as that of the fixed line to become a "Personal Number," second, a cell coverage designed to cover larger areas than that of the PHS (by changing hand-out threshold level from 33 dBµV to 30 dBµV and hand-in threshold level from 30 dBµV to 25 dBµV) in order to reduce the muting time during the handover process and provide higher mobility at up to 60 kilometers per hour, and third, a technique of "2 carriers per area" to reduce "call drop." All these techniques will be described in this paper.

An efficient algorithm for reconstructing all polyhedral 3D objects from two orthographic views is presented. Since the two-view orthographic representation of a 3D object is ambiguous, it requires a numerous amount of combinatorial searches in the process of reconstruction. Also, multiple number of solutions in contrast to the designers intention can be existed in the problem. This paper proposes a two phase algorithm to reduce the search space and to select the most plausible solution described by the given projections. First, the partially constructed objects are reconstructed from the restricted candidate faces corresponding to each area on the two-view drawings in its first phase. Then the complete objects are obtained from the partially constructed objects by adding other candidates with geometrical validity in the second phase. The algorithm performs a combinatorial search based on the face decision rules along with two heuristics. Decision rules check geometrical validity and heuristic rules enhance the search speed. In addition, the reconstruction finds the most plausible 3D object that human observers are most likely to select first among the given multiple solutions. Several examples from a working implementation are given to show the completeness of the algorithm.

After a brief discussion of the demands in meshing for semiconductor process and device simulation, we present a three-dimensional Delaunay refinement technique combined with a modified advancing front algorithm.

In this paper, we investigate the bit error rate (BER) performance of Direct Sequence-Code Division Multiple Access (DS-CDMA) systems under impulsive radio noise environments, and propose a novel DS-CDMA receiver which is designed to be robust against impulsive noise. At first, employing the Middleton's Class-A impulsive noise model as a typical model of impulsive radio noise, we discuss the statistical characteristics of impulsive radio noise and demonstrate that the quadrature components of impulsive noise are statistically dependent. Next, based on the computer simulation, we evaluate the BER performance of a conventional DS-CDMA system under a Class-A impulsive noise environment, and illustrate that the performance of the conventional DS-CDMA system is drastically degraded by the effects of the impulsive noise. To deal with this problem, motivated by the statistical dependence between the quadrature components of impulsive radio noise, we propose a new DS-CDMA receiver which can eliminate the effects of the channel impulsive noise. The numerical result shows that the performance of the DS-CDMA system under the impulsive noise environment is significantly improved by using this proposed receiver. Finally, to confirm the effectiveness of this proposed receiver against actual impulsive radio noise, we evaluate the BER performance of the DS-CDMA system employing the proposed receiver under a microwave oven (MWO) noise environment and discuss the robustness of the proposed receiver against MWO noise.

The current Internet does not offer any quality of service guarantees or support to Internet multimedia applications such as Internet telephony and video-conferencing, due to the best-effort nature of the Internet. Their performance may be adversely affected by network congestion. Also, since these applications commonly employ the UDP transport protocol, which lacks congestion control mechanisms, they may severely overload the network and starve other applications. We present an overview of recent research efforts in developing adaptive delivery models for Internet multimedia applications, which dynamically adjust the transmission rate according to network conditions. We classify the approaches used to develop adaptive delivery models with brief descriptions of representative research work. We then evaluate the approaches based on important design issues and performance criteria, such as the scalability of the control mechanism, responsiveness in detecting and reacting to congestion, and ability to accommodate receiver heterogeniety. Some conclusions are developed regarding the suitability of particular design choices under various conditions.

The full-band Monte Carlo technique is currently the most accurate device simulation method, but its usefulness is limited because it is very CPU intensive. This work describes efficient algorithms in detail, which raise the efficiency of the full-band Monte Carlo method to a level where it becomes applicable in the device design process beyond exemplary simulations. The k-space is discretized with a nonuniform tetrahedral grid, which minimizes the discretization error of the linear energy interpolation and memory requirements. A consistent discretization of the inverse mass tensor is utilized to formulate efficient transport parameter estimators. Particle scattering is modeled in such a way that a very fast rejection technique can be used for the generation of the final state eliminating the main cause of the inefficiency of full-band Monte Carlo simulations. The developed full-band Monte Carlo simulator is highly efficient. For example, in conjunction with the nonself-consistent simulation technique CPU times of a few CPU minutes per bias point are achieved for substrate current calculations. Self-consistent calculations of the drain current of a 60nm-NMOSFET take about a few CPU hours demonstrating the feasibility of full-band Monte Carlo simulations.

Enhancement of resonance is shown by coupling and summing in sinusoidally driven chaotic neural networks. This resonance phenomenon has a peak at a drive frequency similar to noise-induced stochastic resonance (SR), however, the mechanism is different from noise-induced SR. We numerically study the properties of resonance in chaotic neural networks in the turbulent phase with summing and homogeneous coupling, with particular consideration of enhancement of the signal-to-noise ratio (SNR) by coupling and summing. Summing networks can enhance the SNR of a mean field based on the law of large numbers. Global coupling can enhance the SNR of a mean field and a neuron in the network. However, enhancement is not guaranteed and depends on the parameters. A combination of coupling and summing enhances the SNR, but summing to provide a mean field is more effective than coupling on a neuron level to promote the SNR. The global coupling network has a negative correlation between the SNR of the mean field and the Kolmogorov-Sinai (KS) entropy, and between the SNR of a neuron in the network and the KS entropy. This negative correlation is similar to the results of the driven single neuron model. The SNR is saturated as an increase in the drive amplitude, and further increases change the state into a nonchaotic one. The SNR is enhanced around a few frequencies and the dependence on frequency is clearer and smoother than the results of the driven single neuron model. Such dependence on the drive amplitude and frequency exhibits similarities to the results of the driven single neuron model. The nearest neighbor coupling network with a periodic or free boundary can also enhance the SNR of a neuron depending on the parameters. The network also has a negative correlation between the SNR of a neuron and the KS entropy whenever the boundary is periodic or free. The network with a free boundary does not have a significant effect on the SNR from both edges of the free boundaries.

We show by numerical calculations that a chaotic neuron model driven by a weak sinusoid has resonance. This resonance phenomenon has a peak at a drive frequency similar to that of noise-induced stochastic resonance (SR). This neuron model was proposed from biological studies and shows a chaotic response when a parameter is varied. SR is a noise induced effect in driven nonlinear dynamical systems. The basic SR mechanism can be understood through synchronization and resonance in a bistable system driven by a subthreshold sinusoid plus noise. Therefore, background noise can boost a weak signal using SR. This effect is found in biological sensory neurons and obviously has some useful sensory function. The signal-to-noise ratio (SNR) of the driven chaotic neuron model is improved depending on the drive frequency; especially at low frequencies, the SNR is remarkably promoted. The resonance mechanism in the model is different from the noise-induced SR mechanism. This paper considers the mechanism and proposes possible explanations. Also, the meaning of chaos in biological systems based on the resonance phenomenon is considered.

An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, Vgoff and Vgsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.

The change over from IPv4 to IPv6 entails a potential increase in the number of records that the Registry System must maintain. Currently, only a few Network Information Centers (NICs), controlled by Internet Assigned Number Authority (IANA), operate their Registry Systems. As they concentrates data into several Registry System, it is not scalable. This paper focuses on the scalability issue in a Registry System and Mie Advanced Registry System (MARS) is proposed. Through the collaboration of independent Registry Systems, MARS ensures data consistency as well as making it possible to access data managed by other Registry Systems. A prototype system of MARS is implemented, maintained and managed on the WIDE 6bone. Some lessen from the operation of MARS give also described.

Various I/O interface technologies in today's PC platform are classified into four categories, (1) ASIC (memory Controller) from / to Main Memory, (2) MPU from /to ASIC (Memory Controller), (3) ASIC (Memory Controller) from / to ASIC (Graphic Controller) and (4) ASIC from / to Peripherals. As to Category 1, effectiveness of SSTL is shown in DIMM application of SDRAM and DDR SDRAM over 100 MHz frequency. Furthermore a comparison is made between SLDRAM and D- RDRAM from the technology point of view. Concerning Categories 2 through 4, several interfaces such as PCI, AGP, GTL, HSTL and LVDS are reviewed. Interface technologies will keep playing an important role since computer systems require higher and higher speeds.

It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.

This report describes AlGaAs/GaAs HBT ICs for 20-Gb/s optical transmission, the preamplifier and optical modulator driver circuits, and those ICs for 10-Gb/s clock extraction circuits, the rectifier and phase shifter circuits. These ICs were fabricated using our developed hetero guard-ring fully self-aligned HBT (HG-FST) fabrication process. The Pt-Ti-Pt-Au multimetal system was also used as a base ohmic metal to reduce base contact resistance, and a high fmax of 105 GHz was obtained. Good results in the HBT IC microwave performances were achieved from the on-wafer measurements. The preamplifiers exhibited the broad bandwidth of 20. 9 GHz. The optical modulator driver performed a sufficiently large output-voltage swing of 4-VP-P at a 20-Gb/s data rate. The rectifier and the phase shifter circuits achieved good operations at 10-Gb/s. These results suggest that these HBT ICs can be applied to 20-Gb/s optical transmission and 10-Gb/s clock extraction systems.

A direct conversion transmitter IC including a proposed frequency doubler, a quadrature modulator, and a 3-bit variable attenuator was fabricated using BiCMOS technology with fT of 12 GHz. This architecture employing frequency doubler is intended for realizing wireless terminals that are low in cost and small in size. The architecture is effective for reducing serious interference between PA and VCO by making the VCO frequency different from that of PA. The proposed frequency doubler comprises a current-driven 90 phase-shifter and an ECL-EXOR circuit for both low power operation and wide input power range of local oscillator (LO). The proposed frequency doubler keeps high output power even when rectangular wave from LO is applied owing to use of the current-driven 90 phase-shifter instead of a voltage-driven 90 phase-shifter. An LO leakage of less than -25 dBc, an image rejection ratio in excess of 45 dBc, and a maximum attenuation of 21 dB were measured. The transmitter IC successfully operates at LO power above -15 dBm and consumes 68 mA from 2.7 V power supply voltage. An active die size is 1.5 mm3 mm.

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called "switched diffusion analog memory with feedback circuit (FBSDAM). " FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4µm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.

Digital logic frequency detector whose operation is based on the analog quadricorrelator is presented. Proposed circuit consists of conventional digital logic devices without an alog elements. Therefore, it has superior reliabilities over component drifts or aging effects. Frequency linear discrimination range is 100% of the reference clock rate.

A new electromagnetic coupling structure has been proposed for a millimeter wave DR-VCO. The structure consists of a microstrip substrate placed on a planar type dielectric resonator and provides a strongly confined electromagnetic field and a high Q. The resonator used in this structure is a TE010 mode dielectric resonator composed of a dielectric substrate and electrodes on both sides of the substrate. Each electrode has a circular hollow patch. A microstrip circuit substrate with an aperture on the ground electrode is stacked on the resonator. The resonator is magnetically coupled to the transmission line through the aperture. The coupling structure has advantages as follows: (a) The electromagnetic field is strongly confined at the hollow patch, and (b) unloaded Q reduction is only 18% under a strong coupling. When the structure is used as a resonant circuit for a DR-VCO, the circuit can be small because the transmission lines to be isolated from the resonator are able to be placed near the resonator. Both a large loaded Q and a large reflection coefficient of a resonant circuit are obtained with the structure. Fabricated DR-VCO has following performances. The oscillation center frequency is 30. 242 GHz and the frequency tuning range is 91 MHz when the control voltage varies 2 to 10 V. An output power of more than 7.3 dBm and a C/N of 90 dBc/Hz at 100 kHz offset are obtained at the frequency range.

A high performance voltage down converter (VDC) is proposed in this paper. The proposed VDC can automatically control the driving current in seven phases to reduce the fluctuation of output voltage in VDC. By using above new flexible control technology of driving current, the fluctuation of output voltage can be suppressed to less than 10% and the average consuming current of VDC can be suppressed to 34 µA, even if the operation frequency is 200 MHz at the average driving current 100 mA. Therefore, the proposed VDC can operate with large driving current, low-power consumption and good response at the same time. Above all, this technology is very suitable for high perform ULSIs which require large load current, very low-power and high speed operation.

The equivalence between Aperture Field Integration Method (AFIM) and Physical Optical (PO) is discussed for polyhedron surfaces in this paper. The necessary conditions for the equivalence are summarized which demand complete equivalent surface currents and complete apertures. The importance of the exact expressions for both incident and reflected fields in constructing equivalent surface currents is emphasized and demonstrated numerically. The fields from reflected components on additional surface which lies on the Geometrical Optics (GO) reflection boundary are evaluated asymptotically. The analytical expression enhances the computational efficiency of the complete AFIM. The equivalent edge currents (EECs) for AFIM (AFIMEECs) are used to extract the mechanism of this equivalence between AFIM and PO.

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1. 5 µm CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.