The data-driven model of computation is well suited for flexible and highly parallel simulation of neural networks. First, the operational semantics of data-driven languages preserve the locality and functionality of neural networks, and naturally describe their inherent parallelism. Second, the asynchronous data-driven execution facilitates the implementation of large and scalable multiprocessor systems, which are necessary to obtain considerable degrees of simulation sppedups. In this paper, we present a dynamic data-driven multiprocessor system, and demonstrate its suitability for the paralel simulation of back propagation neural networks. Two parallel implementations are described and evaluated using an image data compression network. The system is scalable, and as a result, the performance improved proportionally with the increase in number of processors.

A design rule relaxation approach is one of the most important requirements for high density DRAMs. The approach relaxes the design rule of a element in comparison with the memory cell size and provides high density DRAMs with the minimum development of a scaled-down MOS structure and a fine patterning lithography process. This paper describes two design rule relaxation approaches, a close-packed folded (CPF) bit-line cell array layout and a Boosted Dual Word-Line scheme. The CPF cell array provides 1.26 times wider active area pitch and maximum 1.5 times wider isolation width. The Boosted Dual Word-Line scheme provides 2n times wider 1st Al pitch on memory cell array, double word-line driver pitch and 1.5 times larger design rule for 1st Al and contacts under 1st Al. Especially wide design rule of the Boosted Dual Word-Line scheme provides several times depth of focus (DOF) for 1st Al wiring which gives several times higher storage node and larger capacitance for capacitor over bit-line (COB) stacked capacitor cells. These approaches are successfully implemented in a 4 Mb DRAM test chip with a 0.91.8 µm2 memory cell.

A new evaluation technique of hot carrier degradation is proposed and applied to practical evaluation of p-channel polycrystalline silicon thin film transistors (TFT). The proposed technique introduces emission microscopy which is particularly effective for evaluating TFT devices. We have developed an automatic measurement system in which measurement of the electrical characteristics and monitoring the photo emission are done simultaneously. Using this system, we have identified the dominant mechanism of hot carrier degradation in TFTs, and evaluated the effect of plasma hydrogenation on hot carrier degradation.

Thin (Ba0.75Sr0.25)TiO3 (BST) films to be used as dielectric materials in 256 Mbit DRAM capacitors were investigated. These films were deposited by an rf-sputtering method at substrate temperatures of 480 to 750. As substrate temperature increases, the dielectric constant to the films also increases, from 230 to 550. BST films prepared at temperatures higher than 700 show larger current leaks than films prepared at lower temperatures. A dielectric constant of 250, corresponding to a silicon oxide equivalent thickness (teq) of 0.47 nm, and a leak current density about 110-8 A/cm2 were obtained in 30-nm-thick film deposited at 660. Both of these values are sufficient for use in a 256 Mbit DRAM capacitor.

This paper proposes a datagram delivery (class D service) architecture in an ATM-Internet, which is the network interconnecting ATM-LANs through the IWUs, Inter-Working Unit. We can provide a fast datagram delivery system through the following techniques. The datagram delivery to the destination terminal is performed by the datagram delivery server, so called CLS, which is located in the ATM-LAN where the destination terminal belongs to. Each CLS only manages the addresses for the terminals belonging to the corresponding ATM-LAN. The cells belonging to a certain datagram are transferred through a single (seamless) ATM connection from the source terminal to the CLS in the ATM-LAN where the destination terminal belongs to. The source terminal only resolves the access point address corresponding to the ATM-LAN where the destination terminal belongs to, when it submits the cells to the network to transfer the datagram to the corresponding destination terminal. The proposed datagram delivery architecture can be applied to the ATM-LAN system based on VPI routing architecture, easily. The number of the required ATM connections so as to provide datagram delivery through the proposed architecture is less than 1.0% of the ATM connections that the ATM-Internet can provide. Also, the required address space at UNI to provide datagram delivery are less than 1.0% of the UNI address space which is available to be used as an ATM connection identifier.

A new method for the DRAM soft-error evaluation was developed. By using a focused proton microprobe as a radiation source, and scanning it on a memory cell plane, local sensitive structure of memory cells against soft-errors could be investigated with a form of the susceptibility mapping. Cell mode and bit-line mode soft-errors could be clearly distinguished by controlling the incident location and the proton dose, and it was also found that the incident beam within 4 µm around the monitored memory cell caused the soft-error. The retrograde well formed by the MeV ion implantation technology was examined by this method. It was confirmed that the B+ layers in the retrograde well were a sufficient barrier against the charge collection. The generation rate of the electron-hole pairs and the charge collection into n+ layers with a retrograde well and a conventional well were estimated by the device simulator, and were explained the experimental results.

The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.

A new kind of optical local area network (LAN), using a demand assign wavelength division multiple access (DA-WDMA) scheme, has been proposed. The proposed LAN consists of two parts; an ordinary standardized LAN and an overlaid network using wavelength division (WD) channels. The proposed network can provide bit-rate independent communication channels on the ordinary LAN without limiting the capacities for the other channels. It also exhibits upgrade possibilities from present standardized networks. An access controller, which consists of software in addition to the ordinary LAN controller, a digital signal processor (DSP) etc., was developed for DA-WDMA control. The network node operation has been demonstrated using guided-wave acousto-optic (AO) mode converters as a tunable wavelength add-drop multiplexer (ADM).

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.

Numerical simulation of the hydrodynamic semiconductor device equations requires powerful numerical schemes. A Space-time Galerkin/Least-Squares finite element formulation, that has been successfully applied to problems of fluid dynamic, is proposed for the solution of the hydrodynamic device equations. Similarity between the equations of fluid dynamic and semiconductor devices is discussed. The robustness and accuracy of the numerical scheme are demonstrated with the example of a single electron carrier submicron silicon MESFET device.

This paper describes modeling and simulation of submicron NMOSFET current drive focusing on carrier velocity-saturation effects. A new simple analytical model is proposed which predicts a significant degradation of drain current in sub- and quarter-micron NMOSFET's. Numerical two-dimensional simulations clarify that the degradation is namely caused by high lateral electric field along the channel, which leads to deep velocity-saturation of channel electrons even at the source end. Experimental data of NMOSFET's, with gate oxide thickness (Tox) of 9-20 nm and effective channel lengths (Leff) of 0.35-3.0 µm, show good agreement with the proposed model. It is found that the maximum drain current at the supply voltage of Vdd=3.3 V is predicted to be proportional to Leff0.54 in submicron NMOSFET's, and this is verified with experiments.

The performance of a drift-diffusion device simulator using massively parallel processors is improved by modifying the preconditioner for the iterative solver and by improving the initial guess for the Newton loop. A grid-to-processor mapping scheme is presented to implement the partitioned natural ordering preconditioner on the CM-5. A new preconditioner called the block partitioned natural ordering, which may include fill-ins, improves performance in terms of CPU time and convergence behavior on the CM-5. A multigrid discretization to implement a block Newton initial guess routine is observed to decrease the CPU time by a factor of two. Extensions of the initial guess routine show further reduction in the final fine grid linear iterations.

A software package has been developed for simulating complex silicon and heterostructure devices in 3D. Device geometries are input with a mouse-driven geometric modeler, thus simplifying the definition of complex 3D shapes. Single components of the device are assembled through boolean operations. Tetrahedra are used for grid generation, since any plane-faced geometry can be tessellated with tetrahedra, and point densities can be adapted locally. The use of a novel octree-like data structure leads to oriented grids where desirable. Bad angles that prevent the convergence of the control volume integration scheme are eliminated mostly through topological transformations, thus avoiding the insertion of many redundant grid points. The discretized drift-diffusion equations are solved with an iterative method, using either a decoupled (or Gummel) scheme, or a fully coupled Newton scheme. Alternatively, generated grids can be submitted to a Laplace solver in order to calculate wire capacitances and resistances. Several examples of results illustrate the flexibility and effectiveness of this approach.

This paper discusses the design of an ITS to realize a load-oriented tutoring to enhance the student's explanation understanding. In the explanation understanding, it is to be hoped that a student not only memorizes the new information from an explanation, but also relates the acquired information with his/her own knowledge to recognize what it means. This relating process can be viewed as the one in which the student structures his/her knowledge with the explanation. In our ITS, we regard the knowledge-structuring activities as the explanation understanding. In this paper, we propose an explanation, called a load-oriented explanation, with the intention of applying a load to the student's knowledge-structuring activities purposefully. If the proper load is applied, the explanation can induce the student to think by himself/herself. Therefore he/she will have a chance of gaining the deeper understanding. The important point toward the load-oriented explanation generation is to control the load heaviness appropriately, which a student will bear in understanding the explanation. This requires to estimate how an explanation promotes the understanding activities and how much the load is applied to the activities. In order to provide ITS with the estimation, we have built an Explanation Effect Model, EEM for short. Our ITS consists of an explanation planner and a self-explanation environment. The planner generates the load-oriented explanation based on EEM. The system also makes a student explain the explanation understanding process to himself/herself. Such self-explanation is useful to let the student be conscious of the necessity of structuring his/her knowledge with the explanation. The self-explanation environment supports the student's self-explanation. Furthermore, if the student reaches an impasse in self-explaining, the planner can generate the supporting explanation for the impasse.

Leakage enhancement after an ESD event has been analyzed for output buffer LDD MOSFETs. The HBM ESD failure threshold for the LDD MOSFETs is only 200-300 V and the failure is the leakage enhancement of the off-state MOSFETs called as "soft breakdown" leakage. This leakage enhancement is supposed to be caused by trapped electrons in the gate oxide and/or creation of interface states at the gate overlapped drain region due to snap-back stress during the ESD event. The mechanism of the lekage can be explained by band-to-band and/or interface state-to-band tunneling of electrons. The improvement of the HBM ESD threshold has been also evaluated by using two types of drain engineering which are additional arsenic implantation for the output LDD MOSFETs and "offset" gate MOSFET as a protection circuit for the output pins. By using these drain engineering, the threshold can be improved to more than 2000 V.

Observations of rain depolarization characteristics were conducted using the CS-2 and CS-3 beacon signals (19.45GHz, circular polarization, elevation angle=49.5) during seven years of 1986-1992 at Neyagawa, Osaka. The mean cross-polar phase relative to the co-polar phase of each rainfall event is distributed in a comparatively wide range from -100 to -150. This large variation is suggested to be caused by the difference of raindrop size distribution (DSD) in addition to that of rain intensity. The effects of DSD are examined by rain attenuation statistics for specific months, together with direct measurements of raindrop diameters on the ground for several rainfall events. Compared with representative DSD models, the effects of the Joss-drizzle type with relatively small raindrops primarily appear in "Baiu (Tsuyu)" period, while the effects of the Marshall-Palmer type which represents a standard type are enhanced in "Shurin (Akisame)" period. On the other hand, the effects of the Joss-thunderstorm type with comparatively large raindrops do not indicate a very clear seasonal variation. Possible improvements of XPD performed by differential phase shifters are generally found to be lower than 10dB for the rain depolarization due to the effect of residual differential attenuation after the cancellation of differential phase shift. Such XPD improvements are, however, very sensitive to the type of DSD, and it is suggested that the improvements are at least greater than 6dB for the Joss-drizzle type, whereas they are less than 6dB for the Marshall-Palmer and Joss-thunderstorm types. The effects of the XPD improvements are thus related to rainfall types, i.e., the type of DSD, and the improvements are considerably dependent upon the seasons in which each rainfall type frequently appears.

Automotive electronics technology has become extremely advanced in the regions of automotive engine control, anti-skid brake control, and others. These control systems require highly advanced control performance and high speed microprocessors which can rapidly execute interrupt processing. Automotive engine control systems are now widely utilized in cars with high speed, high power engines. At present, it is generally acknowledged that such high performance engine control for the 10,000 rpm, 12 cylinder engines requires three or more conventional microprocessors. We fabricated an engine control system prototype incorporating the data-driven processor under development, which was installed in an actual automobile. In this paper, the characteristics of the engine control program and simulation results are firstly discussed. Secondly, the structure of the engine control system prototype and the control performance applied to the actual automobile are shown. Finally, from the results of software simulation and the installation of the engine control system prototype with the data-driven processor, we conclude that a single chip data-driven microprocessor can control a high speed, high power, 10,000 rpm, 12 cylinder automobile engine.

Since carelessness in driving causes a terrible traffic accident, it is an important subject for a vehicle to avoid collision autonomously. Real-time collision detection between a vehicle and obstacles will be a key target for the next-generation car electronics system. In collision detection, a large storage capacity is usually required to store the 3-D information on the obstacles lacated in a workspace. Moreover, high-computational power is essential not only in coordinate transformation but also in matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a Content-Addressable Memory (CAM) which evaluates the magnitude relationships between an input word and all the stored words in parallel. A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be parformed only by parallel magnitude comparison. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. The collision detection time becomes 5.2 ms using 20 PEs and five CAMs with a 42-kbit capacity.

Electronics and automobiles were bound together by the introduction of emission regulations in the 1970's. The rapid progress of control technology and semiconductors that typify microcomputers has brought still closer relations between them. Without electronics, it would be impossible to realize features such as pursuit of comfort and environmental and safety measures which should be added to the automobile's fundamental features. In looking ahead to the future, the role of electronics in achieving electric automobiles and the ultimate goal of "automatic driving" is ever-increasing. Everyone knows that automobiles have become indispensable in our lives. In the future, the role of electronics will become increasingly important in order to evolve automobiles even further to allow harmonization with society.