In this paper, we extend two-image photometric stereo method to treat a concave polyhedron, and present an iterative algorithm to remove the influence of interreflections. By the method we can obtain the shape and reflectance of a concave polyhedron with perfectly diffuse (Lambertian) and unknown constant reflectance. Both simulation and experiment show the feasibility and accuracy of the method.

In this paper we estimate the number of permutations realizable in fault-tolerant multistage interconnection networks designed to tolerate faults on any switching element. The Parallel Omega network and the INDRA network are representative types of fault-tolerate multistage interconnection networks designed to tolerate a single fault. In order to evaluate the enhancement in the function of network by preparing the hardware redundancy for fault-tolerance, we estimate the number of permutations realizable in fault-tolerant networks. This result enables us to set up a standard to evaluate the hardware redundancy required to tolerate multifaults from the viewpoint of the enhancement of network function. This paper concludes that in the case where the number of inputs is up to 32 the increase ratio of the number of realizable permutations is no more than 1/0.73 even if the tolerance to multifaults is prepared instead of the tolerance to a single fault.

Radar signals fluctuate because of the incoherent scattering of raindrops. Dual-polarization radar estimates rainfall rates from differential reflectivity (ZDR) and horizontal reflectivity (ZH). Here, ZDR and ZH are extracted from fluctuating radar signals by averaging. Therefore, instrumentally measured ZDR and ZH always have errors, so that estimated rainfall rates also have errors. This paper evaluates rainfall rate errors caused by signal fluctuation. Computer simulation based on a physical raindrop model is used to investigate the standard deviation of rainfall rate. The simulation considers acquisition time, and uses both simultaneous and alternate sampling of horizontal and vertical polarizations for square law and logarithmic estimators at various rainfall rates and elevation angles. When measuring rainfall rates that range from 1.0 to 10.0mm/h with the alternate sampling method, using a logarithmic estimator at a relatively large elevation angle, the estimated rainfall rates have significant errors. The simultaneous sampling method is effective in reducing these errors.

This paper describes the architecture and new circuit technologies of a proposed Pixel (bit) -Aligned Triple-port DRAM (PATDRAM). The PATDRAM has a 270 K word 16 b Random Access Memory (RAM), a 512 word 8 b Serial Access Memory-(a) (SAMa) and a 1024 word 4 b Serial Access Memory-(b) (SAMb). The random port, serial-a and serial-b port can be operated by three independent synchronous clocks. In these three ports, word data can be aligned to the location of an arbitrary bit position. Data transfer from SAMb to RAM can be individually masked by transfer mask data. The RAM operates by 33 MHz synchronous clock and two SAMs operate by 40 MHz clocks. Novel architecture of the PATDRAM accelerates graphics performance and simplifies in multimedia systems which manage both realtime video and computer graphics data, and also accelerates graphics performance in both two-dimensional (2D) and three-dimensional (3D) graphics systems. PATDRAM was designed using a 0.6 µ double metal, triple poly, stacked capacitor, CMOS process technology in a 10.98 mm9.88 mm die area integrated 4.4 Mb RAM, 8 Kb SAM, 4 Kb transfer mask register and 5 Kgate logic.

The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.

A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlOx/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO2 insulators. The Nb/AlOx/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.

A distributive serial multi-bit parallel test scheme for large capacity DRAMs has been developed. The scheme, distributively and serially, extracts and compares the data from cells on a main word-line. This test scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM, the scheme successfully has achieved a 512-bit parallel test.

New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.

The magnitude of low frequency noise is studied in a Nb-(nanoconstrictions)-NbN system with adjustable current-voltage characteristics. We find that the magnitude of low frequency noise decreases sharply with increasing the subgap conductivity of the device. We suggest a qualitative explanation of this observation in terms of gradual build up of the nanoconstriction region by field assisted growth. The decrease of low frequency noise is related to the "cleanliness" of the system as measured by the amount of Andreev reflection-related conductivity. The scaling of the magnitude of low frequency noise with device resistance is also discussed.

This paper propeses a new motion compensation (MC) technique which reduces blurring called drift in moving pictures down-scaled with layered coding system. Encoder of the system compresses large amounts of digital video data in the same way of MPEG (Moving Picture Experts Group) algorithm. Decoder, on the other hand, expands a part of the compressed data and reconstructs down scaled pictures. The purpose of this paper is to reduce blurring which is observed in the reconstructed pictures. In this paper, cause of the blurring is analyzed and the method is introduced as a solution to the problem. The new method is implemented by a little modification of motion compensation (MC) of the decoder, namely increasing the number of tap of interpolation fillters of the MC. Compressing moving pictures, its effectiveness is also confirmed by means of not only subjective test but also signal to noise ratio.

This paper presents a new line extraction method to capture vectors based on contours and skeletons from line drawing raster images in which the lines are touched by characters or other lines. Conventionally, two line extraction methods have generally been used. One is a thinning method. The other is a medial line extraction method based on parallel pairs of contours. The thinning method tends to distort the extracted lines, especially at intersections and corners. On the other hand, the medial line extraction method has a poor capability as regards capturing correct lines at intersections. Contours are able to maintain edge shapes well, while skeletons preserve topological features; thus, a combination of these features effectively leads to the best fitting line. In the proposed method, the line which best fits the original image is selected from among various candidate lines. The candidates are created from several merged short skeleton fragments located between pairs of short contour fragments. The method is also extended to circular arc fitting. Experimental results show that the proposed line fitting method is effective.

It is of significantly importance in relation to the problem of diagnosis of deviation faults in linear analog circuits to check whether or not it is possible to uniquely determine the element-values in a given linear analog circuit from the node-voltage measurements at its accessible nodes and then of giving a method for actual computation of the element-values if it is possible, under the assumption that i) the circuit is of known topology (and of known element-kinds if possible) and ii) the actual value of each element-value of the circuit almost always deviates from the design value and is not known exactly. In this paper, the problem of checking the unique determinability of the element-values is called the element-value determinability problem, and its solutions which have been obtained until now are reviewed in perspectives to designing a publicly available user-oriented analog circuit diagnosis system.

An efficient algorithm is presented for solving nonlinear resistive networks. In this algorithm, the techniques of the piecewise-linear homotopy method are introduced to the Katzenelson algorithm, which is known to be globally convergent for a broad class of piecewise-linear resistive networks. The proposed algorithm has the following advantages over the original Katzenelson algorithm. First, it can be applied directly to nonlinear (not piecewise-linear) network equations. Secondly, it can find the accurate solutions of the nonlinear network equations with quadratic convergence. Therefore, accurate solutions can be computed efficiently without the piecewise-linear modeling process. The proposed algorithm is practically more advantageous than the piecewise-linear homotopy method because it is based on the Katzenelson algorithm that is very popular in circuit simulation and has been implemented on several circuit simulators.

Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capasity is usually required to store the 3-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential in not only coordinate transformation but also matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory (CAM). A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed by only magnitude comparison in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 90 ms.

A semicylindrical microstrip applicator system is proposed and designed, both for microwave heating and for noninvasive temperature estimation, in application to hyperthermia treatment. The experimental results showed that the system functions both as a heating device and as a means of noninvasive temperature estimation. Therefore, electrical switching of these two functions makes the system realize both heating and temperature estimation. These functions reduce the pain of hyperthermia therapy for patients. The system is constructed of a water-loaded cylindrical applicator. Thus, the whole system can be made compact compared to conventional applicators. This improvement allows for various merits, such as realizing a surface cooling effect and decreased leakage of electromagnetic (EM) waves. When the applicator is set as an array arrangement, the system can be used as a microwave heating device. The penetration depth can be varied by adjusting phases of the EM wave radiated from each applicator. The experimental results at 430 MHz showed that semicylindrical microstrip applicators can be expected to be valid for tumor heating at depths within 55 mm. Moreover, by measuring transmission power between the two applicators, the system can be used to estimate temperature inside the medium. The transmission power which was measured in the frequency domain was converted in the time domain. By such a method, temperature distribution was calculated by solving simple simultaneous primary equations. The results of the temperature estimation show that the number of estimated temperature segments which have an error within 0.5 is 28 out of 36. The system can be easily used as a temperature measuring applicator as well as a heating applicator.

A kind of time domain reflectometry using deconvolution and envelope extraction process is presented for measuring microwave resonator characteristics, where data acquisition and data processing are performed entirely in the time domain. The proposed method may be used to characterize resonators which have Q values in the range between a few dozen and several hundred. The major drawback of the time domain measurement techniques is in general considered to be a low frequency resolution. In the proposed method, it is avoided skillfully.

An experimental SAR (Specific Absorption Rate) estimation system based upon the thermograph method using a thermograph camera and newly developed homogeneous dry-phantom human models are presented. Experiments are conducted using this system and UHF fields to obtain SAR distributions in the human head irradiated by hand-held portable radios. Experiment results show that the estimated peak SAR's due to the radiation waves from radios of 1W transmitting power are lower than 2W/kg and so conform to the recommendations of the radio-frequency radiation safety guidelines. The developed system enables the surface SAR distributions on the phantom model to be precisely estimated; a function not available with the original system. System parameters required for providing precise estimations are discussed first, and then experiments are conducted to estimate SAR's in the human head exposed to a UHF hand-held portable radio's near field. Finally, estimated data are examined from the viewpoint of radio-frequency exposure safety guidelines.