In this paper, we report a new approach about parsing and searching problem for a given phonetic lattice. The approach is based on the Divide and Conquer (DC) strategy. By dividing the phonetic lattice, we first construct a PD-tree to represent this lattice, then, we parse through this PD-tree to identify the possible sentence which is supposed to be the speech utterance. Next, we propose a new search scheme called Downward Request (DR) search model to decrease the computation costs, and this search model gives us the optimal or N-best solutions. Experiments performed on Chinese speech recognition show us the good results.

This paper presents a new microprocessing method that uses a Cl2 fast atom beam (FAB) with stainless steel (SUS304) patterned masks. This new method uses the patterned mask instead of lithographically processed patterned photoresist materials employed in the conventional FAB microprocessing method. We examined the performance of this method by etching GaAs workpieces under various conditions: (1) by setting the distance between the mask surface and flat workpiece surface, L, from 0 µm to 500 µm; (2) by setting the angle between the FAB axis and the flat workpiece surface, θ; to either 30or 50. (3) by etching a workpiece surface that had a 15-µm step and two different surface textures, smooty and undulated; and (4) by doing overlapped etching using a square-patterned mask first and then a circular-patterned mask. The experiments show that the accuracy of reproducing the mask pattern on the etched surface increases with decreasing L. Moreover, the etching rate is almost the same (L100 µm) and decreases slightly at longer distance (L100 µm). The experiments also show that the side walls of the surface are parallel to the FAB axis, even for θ0, indicating that anisotropic etching can be achieved. The experiments for the stepped surface with different surface textures show the surface texture is not affected by the FAB etching. The overlapped etching experiments show that FAB etching is capable of producing overlapped structures. These results demonstrate that this new FAB method can be used in the microproduction of multi-faced, overlapped, three-dimensional microstructures.

A beam adaptive frame for finite-element beam-propagation analysis is proposed. The width of the frame can be adapted itself to either the guiding structure or the propagating beam in optical circuits, so the size of the computational window can be reduced.

A new type of variable beam splitter at optical frequencies is proposed. The basic structure of the device utilizes a tapered velocity coupler which is composed of a center slab waveguide of constant-thickness, constant-index type and two identical outer slab waveguides of constant-thickness, variable-index type. The coupler is assumed to be fabricated on a LiNbO3 substrate, whith an external electric field applied in parallel with the optical axis. The numerical results obtained with the finite difference method show that a wide range of splitting ratios can be obtained with moderate drive voltages and that the splitting characteristics are stable over a wide range of frequencies.

A method is presented for reconstructing the surface profile of a perfectly conducting rough surface boundary from the measurements of the scattered far-field. The proposed inversion algorithm is based on the use of the Kirchhoff approximation and in order to determine the surface profile, the Fletcher-Powell optimization procedure is applied. A number of numerical results illustrating the method are presented.

We have systematically studied the characteristics of Si doping in GaAs grown on (311)A GaAs substrates by molecular beam epitaxy. The growth temperature dependence of Si doping has been investigated. It is found that the conduction-type sharply changes from p-type to n-type with decreasing growth temperature at a critical temperature of 430-480. The highest hole density obtained for uniformly doped layers was 1.51020 cm-3, while for δ-doped layers the sheet hole density as high as 2.61013 cm-2 was achieved. This is the highest hole density ever reported for δ-doped GaAs.

We propose a beam tracing frame which shifts together with either the guiding structure or the beam propagation in optical circuits. This frame is adaptive to the beam propagation analysis based on the finite-element method and can reduce the computational window size.

Electrical and optical properties of organic multilayer structure have been investigated. Two types of current-voltage characteristics have been found for thin multilayer structure of organic films. Optical property and its application for electroluminescent diode have been presented. The diode characteristics have been discussed in terms of energy band scheme.

A Direct Radiating Array Antenna (DRAA) concept has been introduced to international satellite communications in order to achieve multiple shaped beams which are electrically reconfigurable. The subject of this paper is to describe the new design method for a reconfigurable DRAA. The design procedure consists of three steps, 1) derivation of the initial array layout using Fourier transform method (FTM) , 2) array shape rearrangement, 3) optimization of the final array excitation with the modified constraint least mean square (MCLMS) algorithm. At the first step, it is necessary to derive the initial array layout for the desired shaped beam with respect to array shape, number of antenna elements, and excitation distribution. For this purpose, a new closed form solution of FTM using N-polygonal desired coverage is used. At the second step, the array shape is rearranged to fit the beam forming network (BFN) configuration which can reduce insertion loss and influence on frequency variation sensitivity. At the third step, the array excitation is optimized using MCLMS which is exploited to satisfy the power sum constraints caused by the restriction of the BFN configuration. The design method provides useful insight regarding the layout design of a DRAA with well-shaped coverages, the low insertion loss of the BFN and the high sidelobe isolation characteristic. The design of the reconfigurable DRAA with the specified multiple shaped (beams is demonstrated and compared with the experimental model.

Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation date also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.

We describe a geometrical optics approach for the analysis of dielectric tapered waveguides. The method is based on the ray-optical treatment for wave-normal rays defined newly to waves of light in open structures. Geometrical optics fields are represented in terms of two kinds of wave-normal rays: leaky rays and guided rays. Since the behavior of these rays is different in the two regions separated at critical incidence, the geometrical optics fields have certain classes of discontinuity in a transition region between leaky and guided regions. Guided wave solutions are given as a superposition of guided rays that zigzag along the guides, all of which are totally reflected upon the interfaces. By including some leaky rays adjacent to the guided rays, we obtain more accurate guided wave solutions. Calculated results are in excellent agreement with wave optics solutions.

A new image-based diagnostic method is proposed for use with an E-beam tester. The method features a static fault imaging technique and a navigation map for fault tracing. Static Fault imaging with a dc E-beam enables the fast acquisition of images without any additional hardware. Then, guided by the navigation map derived from CAD data, marginal timing faults can be easily pinpointed. A statistical estimation of the average count of static fault images for various LSI circuits shows that the proposed method can diagnose marginal faults by observing less than thirty faulty images and that a faulty area can be localized with up to five times fewer observations than with the guided-probe method. The proposed method was applied to a 19k-gate CMOS-logic LSI circuit and a marginal timing fault was successfully located.

Recent developments and case studies regarding VLSI device chip failure analysis are reviewed. The key failure analysis techniques reviewed include EMMS (emission microscopy), OBIC (optical beam induced current), LCM (liquid crystal method), EBP (electron beam probing), and FIB (focused ion beam method). Further, future possibilities in failure analysis, and some promising new tools are introduced.

Following a discussion of various testing methods used in the electron beam (EB) test system, new waveform-based and image-based approaches in the CAD-linked electron beam (EB) test system are proposed. A waveform-based automatic tracing algorithm of the transistor-level performance faults is first discussed. Then, the method to improve the efficiency of an image-based method called dynamic fault imaging (DFI) by fully utilizing the CAD data is described. Third, the VLSI development cost is analyzed by using the fault models that make possible to take into consideration the effect of new testing technologies such as EB testing and focused ion beam (FIB) microfabrication. Finally, the future prospects are discussed.

A method to improve the efficiency of dynamic fault imaging (DFI) by fully utilizing the CAD data in the CAD-linked electron beam test system is proposed. In the method, in order to shorten the long acquisition time of the stroboscopic voltage contrast images over the whole area of the chip during the entire test cycle, only the area and phase (time) required for fault tracing are selected by utilizing the CAD data. Furthermore, image processing techniques are combined with the method to improve the efficiency of the DFI. In particular, the signal averaging technique is used in order to improve the signal-to-noise ratio in the stroboscopic images where all voltage information data on the equipotential electrode recognized by the CAD layout data are averaged. This enables us to reduce the acquisition time of images. Moreover, the experimental system is set up so that the image processing can be performed in parallel with the acquisition of the stroboscopic images. The proposed method is applied to part of a 2k-transistor block of a nonpassivated CMOS LSI where a marginal fault is detected. The result shows that the method is an efficient approach to the fully automatic fault diagnosis in the CAD-linked electron beam test system. The proposed method could improve the efficiency of the conventional DFI by a factor of more than 1000.

Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.

An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.

An electron beam cell projection system has been developed that can effectively expose the fine, demagnified resultant pattern of repeated and non-repeated patterns such as the 256 Mb DRAM on a semiconductor wafer. Particular attention was given to the beam shaping and deflecting optics, which has two stage deflectors for the cell projection beam selection as well as the beam sizing, and three stage deflectors for objective deflection. The cell mask with a rectangular aperture and multiple figure apertures is fabricated by modified Si wafer processes. A new exposure control data for the cell projection is proposed. This data is fitted for the combination of pattern data for the cell mask projection and pattern data for the variable rectangular shape beam within the divided units of the objective deflection. On this exposure system, selective exposure of the desired pattern becomes possible on the semiconductor wafer while a mounting stage of the wafer is being moved, even if the pattern exposure of the repeated and non-repeated patterns is to be carried out. The total overhead time for selecting a subset of multiple figures and a rectangular aperture of the cell mask is less than 5 seconds/wafer. The estimated throughput of this system is approximately 20 wafers/hour.

An HDTV still-picture camera that uses four PAL CCD sensors has been developed for use as a high-speed, high-resolution image reader. The CCD sensors are optically coupled to a single lens by a pyramidal mirror. Each CCD sensor reads a quarter of the image and the four quarter-images are combined into one HDTV picture. Discontinuities at the lines where the four images join can be eliminated by white- and dark-level correction and gamma correction. Moreover, smoothing processing using a weighted-mean method is performed to produce a seamless picture. With this processing the camera can consistently produce seamless pictures.

Material representations and algorithms are presented for simulation of nanometer lithography. Organic polymer resists are modeled as collections of overlapping spheres, with each sphere representing a polymer chain. Exposure and post-exposure bake steps are modeled at the nanometer scale for both positive and negative resists. The development algorithm is based on the Poisson removal probability for each sphere in contact with developer. The Poisson removal rate for a given sphere is derived from a mass balance relationship with a macroscopic development rate model. Simulations of electron beam lithography with (poly) methyl methacrylate and Shipley SAL-601 reveal edge roughness standard deviations from 2 to 3 nm, leading to linewidth peak-to-peak 3σ variation of 15 to 22 nm. Typical simulations require about 2 MBytes and under 5 minutes on a Sun Sparc 10/41 engineering workstation.