A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

Asymmetric Slope Dual Mode Differential Logic (ASDMDL) embodies high-speed dynamic and low-power static operations in a single design. Two-phase dual-rail logic signaling is used in a high-speed operation, where a logical evaluation is preceded by pre-charge, and it asserts one of the rails with an asymmetrically shortened rise transition to express a binary result. On the other hand, single-phase differential logic signaling eliminates pre-charge and leads to a low-power static operation. The operation mode is defined by the logic signaling styles, and no control signal is needed in the logic cell. The design of mixed CMOS and ASDMDL logic circuits can be automated with general logic synthesis and place-and-route techniques, since the physical ASDMDL cell is prepared in such a way to comply with a CMOS standard-cell design flow. A mixed ASDMDL/CMOS micro-processor in a 0.18-µm CMOS technology demonstrated 232 MHz operation, corresponding to 14% speed improvement over a full CMOS implementation. This was achieved by substituting ASDMDL cells for only 4% of the CMOS logic cells in data paths. The low-speed operation of ASDMDL at 100 MHz was nearly equivalent to that of CMOS. However, power consumption was reduced by 3% due to the use of ASDMDL complex logic cells. Area overhead was less than 4%.

This paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binary-weighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below 0.5 LSB and that the settling time after the output current mirror is below 12 ns. Although the proposed IDAC architecture was designed for a BMLD chip, the design concept is generic and can be applied for developing other monotonic high-speed current-mode DACs.

This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

Multipath routing employs multiple parallel paths between the source and destination for a connection request to improve resource utilization of a network. In this paper, we present an integrated design of multipath routing with delay constraints and failure survivability in MPLS networks. By combining the failure survivability schemes into the multipath routing algorithms, path protection or restoration policies will enable the network to accommodate link failures and at the same time achieve significant improvement on network resource utilization. We propose a number of multipath routing algorithms, working-backup path selection and bandwidth allocation schemes. We evaluate the performance of the proposed schemes in terms of call blocking probability, network resource utilization and load balancing factor. Extensive simulation results validate the effectiveness of the proposed schemes. In particular, we compare these multipath schemes to the existing failure recovery schemes that mostly focus on single path routing. The results demonstrate that the proposed integrated design framework can provide effective network failure survivability, and also achieve better load balancing and/or higher network resource utilization.

Key agreement for collaborative groups has become an increasingly popular research area. However, most of previous work requires each member to not only maintain the whole key tree structure whose size is O(N), where N is the size of group, but also involve rekeying operation upon each membership change, resulting in high costs in terms of storage, communication and computation and thus suffers from poor scalability. In this paper, we propose a scalable Distributed and collaborative group key agreement scheme using a Virtual Key Tree (D-VKT). Each group member in D-VKT only reserves and maintains partial information of the whole key tree structure with requirement of O(log N). Furthermore, a distributed tree balancing algorithm is presented to keep the whole key tree as balanced as possible for rekeying efficiency. In addition, a distributed group batch rekeying protocol is proposed to further reduce the computation and communication workload of group rekeying in a highly dynamic environment. The experiment results demonstrate that D-VKT can scale to large and dynamic collaborative groups.

Existing standard speech coders can provide high quality speech communication. However, they tend to degrade the performance of automatic speech recognition (ASR) systems that use the reconstructed speech. The main cause of the degradation is in that the linear predictive coefficients (LPCs), which are typical spectral envelope parameters in speech coding, are optimized to speech quality rather than to the performance of speech recognition. In this paper, we propose a speech coder using mel-frequency cepstral coefficients (MFCCs) instead of LPCs to improve the performance of a server-based speech recognition system in network environments. To develop the proposed speech coder with a low-bit rate, we first explore the interframe correlation of MFCCs, which results in the predictive quantization of MFCC. Second, a safety-net scheme is proposed to make the MFCC-based speech coder robust to channel errors. As a result, we propose an 8.7 kbps MFCC-based CELP coder. It is shown that the proposed speech coder has a comparable speech quality to 8 kbps G.729 and the ASR system using the proposed speech coder gives the relative word error rate reduction by 6.8% as compared to the ASR system using G.729 on a large vocabulary task (AURORA4).

To analyze the saturation performance of IEEE 802.11 DCF, several discrete-time Markov chain models for a station and sets of channel equations have been introduced. We take into account a frame retry limit, freezing of backoff counter, and the dependence of backoff procedure on the previous channel status all together. Our method is simple even though it is accurate under the assumption of no consecutive transmissions over the shared channel.

In nature an unbalanced clock tree exists in a SoC because the clock sinks of IPs have distinct input capacitive loads and internal delays. The construction of a bottom-up RLC clock tree with minimal clock delay and zero skew is crucial to ensure good SoC performance. This study proves that an RLC clock tree construction always has no zero skew owing to skew upward propagation. Specifically, this study proposes the insertion of two unit-size buffers associated with the binary search for a tapping point into each pair of subtrees to interrupt the non-zero skew upward propagation. This technique enables reliable construction of a buffered RLC clock tree with zero skew. The effectiveness of the proposed approach is demonstrated by assessing benchmarks.

In this paper, we address how to construct efficient retransmission trees for reliable multicast. Efficiency of retransmission trees mainly depends on locations of repairers, which are in charge of retransmitting lost packets. We propose an algorithm for each receiver to find a repairer for efficient recovery. The resulting tree for retransmission is organized by pairs of a receiver and a repairer which is the host "nearest" to the receiver among the multicast group members "nearer" to the sender. We formally prove that the proposed algorithm realizes reliable multicast with only constant times of a lower bound cost achievable through impractical router support. We also evaluate the algorithm through extensive simulations.

Local weight distribution is the weight distribution of minimal codewords in a linear code. We give the local weight distribution of the (256, 93) third-order binary Reed-Muller code. For the computation, a coset partitioning algorithm is modified by using a binary shift invariance property. This reduces the time complexity by about 1/256 for the code. A necessary and sufficient condition for minimality in Reed-Muller codes is also presented.

In this paper, the authors propose a circularly polarized printed antenna combining a slot array antenna and a patch antenna, with dual-band operation. The proposed antenna has good isolation performance, is compact, and has simple configuration. This antenna is composed of two parts, a patch antenna (for Rx) on the top, and a slot array antenna (for Tx) on the bottom, respectively. The element layout is such that the lower radiation element is not hidden by the upper one for wide observation angle. Hence, both radiation elements can naturally radiate the targeted polarization. Both slot array and patch antenna are fed by electromagnetically coupled microstrip line feed. With such a configuration, it is possible to efficiently obtain good isolation characteristics for both frequency bands. Furthermore, this antenna can be easily composed and it is not necessary to use any feeding pin or via hole. The target of this antenna is mobile communications applications such as mobile satellite communications, base-station of wireless LAN, etc. Here, the design techniques are discussed and the numerical and experimental analyses are presented.

This paper describes the explicit modeling of a state duration's probability density function in HMM-based speech synthesis. We redefine, in a statistically correct manner, the probability of staying in a state for a time interval used to obtain the state duration PDF and demonstrate improvements in the duration of synthesized speech.

In this letter, we propose a limited feedback precoding scheme based upon grassmannian beamforming and user selection for downlink multiuser MIMO systems. Conventional random beamforming scheme only enjoys significant performance gains with a large number of users, which limits its practical application. With proper codebook size the proposed scheme outperforms conventional random beamforming scheme when the number of users is small or moderate.

This paper describes an 11-Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is received to serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX consists of eight integrators. The DEMUX is designed with 0.35 µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43 mW. This circuit is expected to operate at higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.

In real-time speech recognition applications, there is a need to implement a fast and reliable adaptation algorithm. We propose a method to reduce adaptation time of the rapid unsupervised speaker adaptation based on HMM-Sufficient Statistics. We use only a single arbitrary utterance without transcriptions in selecting the N-best speakers' Sufficient Statistics created offline to provide data for adaptation to a target speaker. Further reduction of N-best implies a reduction in adaptation time. However, it degrades recognition performance due to insufficiency of data needed to robustly adapt the model. Linear interpolation of the global HMM-Sufficient Statistics offsets this negative effect and achieves a 50% reduction in adaptation time without compromising the recognition performance. Furthermore, we compared our method with Vocal Tract Length Normalization (VTLN), Maximum A Posteriori (MAP) and Maximum Likelihood Linear Regression (MLLR). Moreover, we tested in office, car, crowd and booth noise environments in 10 dB, 15 dB, 20 dB and 25 dB SNRs.

In this paper, a recognition algorithm for the class of tree languages generated by linear, monadic context-free tree grammars (LM-CFTGs) is proposed. LM-CFTGs define an important class of tree languages because LM-CFTGs are weakly equivalent to tree adjoining grammars (TAGs). The algorithm uses the CKY algorithm as a subprogram and recognizes whether an input tree can be derived from a given LM-CFTG in O(n4) time, where n is the number of nodes of the input tree.

We consider a problem for constructing a minimum cost r-edge-connected multigraph in which degree d(v) of each vertex v ∈ V is specified. In this paper, we propose a 3-approximation algorithm for this problem under the assumption that edge cost is metric, r(u,v) ∈ {1,2} for each u,v ∈ V, and d(v) ≥ 2 for each v ∈ V. This problem is a generalization of metric TSP. We also propose an approximation algorithm for the digraph version of the problem.

Let G be any graph with property P (for example, general graph, directed graph, etc.) and S be nonnegative and non-decreasing integer sequence(s). The prescribed degree sequence problem is a problem to determine whether there is a graph G having S as the prescribed sequence(s) of degrees or outdegrees of the vertices. From 1950's, P has attracted wide attentions, and its many extensions have been considered. Let P be the property satisfying the following (1) and (2):(1) G is a directed graph with two disjoint vertex sets A and B. (2) There are r11 (r22, respectively) directed edges between every pair of vertices in A(B), and r12 directed edges between every pair of vertex in A and vertex in B. Then G is called an (r11, r12, r22)-tournament ("tournament", for short). The problem is called the score sequence pair problem of a "tournament" (realizable, for short). S is called a score sequence pair of a "tournament" if the answer of the problem is "yes." In this paper, we propose the characterizations of a score sequence pair of a "tournament" and an algorithm for determining in linear time whether a pair of two integer sequences is realizable or not.

A novel configuration method called Row Multicast Configuration (RoMultiC) is proposed for high speed configuration of coarse grain reconfigurable systems. The same configuration data can be transferred in multicast fashion to configure many Processing Elements (PEs) by using a multicast bit-map provided in row and column directions of PE array. Evaluation results using practical applications show that a model reconfigurable system that incorporates this scheme can reduce configuration clock cycles by up to 73.1% compared with traditional configuration delivery scheme. Amount of required memory to store the configuration data at external memory is also reduced by omitting the duplicated configuration data.