This paper describes the efficiency-limiting factors resulting from transistor current source in the case of class-F and inverse class-F (F-1) operations under saturated region. We investigated the influence of knee voltage and gate-voltage clipping behaviors on drain efficiency as limiting factors for the current source. Numerical analysis using a simplified transistor model was carried out. As a result, we have demonstrated that the limiting factor for class-F-1 operation is the gate-diode conduction rather than knee voltage. On the other hand, class-F PA is restricted by the knee voltage effects. Furthermore, nonlinear measurements carried out on a GaN HEMT validate our analytical results.

The major task in compact modeling for high power devices is to predict the switching waveform accurately because it determines the energy loss of circuits. Device capacitance mainly determines the switching characteristics, which makes accurate capacitance modeling inevitable. This paper presents a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for Gallium-Nitride-based High Electron Mobility Transistors (GaN-HEMTs)], where the focus is given on the accurate modeling of the field-plate (FP), which is introduced to delocalize the electric-field peak that occurs at the electrode edge. We demonstrate that the proposed model reproduces capacitance measurements of a GaN-HEMT accurately without fitting parameters. Furthermore, the influence of the field plate on the studied circuit performance is analyzed.

A wide-bandwidth fundamental mixer operating at a frequency above 110GHz for precise spectrum analysis was developed using the InP HEMT technology. A single-ended resistive mixer was adopted for the mixer circuit. An IF amplifier and LO buffer amplifier were also developed and integrated into the mixer chip. As for packaging into a metal block module, a flip-chip bonding technique was introduced. Compared to face-up mounting with wire connections, flip-chip bonding exhibited good frequency flatness in signal loss. The mixer module with a built-in IF amplifier achieved a conversion gain of 5dB at an RF frequency of 135GHz and a 3-dB bandwidth of 35GHz. The mixer module with an LO buffer amplifier operated well even at an LO power of -20dBm.

We investigated the influence of the thickness of the AlN interlayer for InAlN/GaN and InAlN/AlGaN/GaN heterostructures. The AlN thickness strongly affects the surface morphology and electron mobility of the InAlN/GaN structures. The rms roughness of the surface increases from 0.35 to 1.2 nm with increasing AlN thickness from 0 to 1.5 nm. Large pits are generated when the AlN is thicker than 1 nm. The highest electron mobility of 1470 cm2/VS is obtained for a 0.75-nm-thick AlN interlayer. The mobility, however, becomes lower with increasing deviation from 0.75 nm. It is only 200 cm2/VS for the 0-nm thick AlN. Inserting AlGaN between AlN and InAlN suppresses the influence of the AlN interlayer thickness. A smooth surface with rms roughness of 0.35 nm is obtained for all samples with 0-1.5-nm-thick AlN. The electron mobility ranges from 1000 to 1690 cm2/VS. The variation is smaller than that for InAlN/GaN. We fabricated field effect transistors (FETs) with gate length of 2 µm. The electron mobility in the access region affects the transconductance (gm) of FETs. As a results, the influence of the AlN thickness for InAlN/GaN FETs is larger than that for InAlN/AlGaN/GaN FETs, which reduces gate leakage current. The transconductance varies from 93 to 235 mS/mm for InAlN/GaN FETs. In contrast, it varies from 180 to 230 mS/mm for InAlN/AlGaN/GaN FETs. These results indicate that the InAlN/AlGaN/GaN heterostructures could lead to the development of GaN-based FETs.

Current collapse phenomenon is a well known obstacle in the AlGaN/GaN HEMTs. In order to improve the surface stability of HEMTs, we have investigated the SiN passivation film deposited by T-CVD, and we found that it improves both gate leakage current and current collapse phenomenon [1]. Moreover, we compared the T-CVD and PE-CVD passivation films, on high electric field DC and RF characteristics. We found that T-CVD SiN passivation film improves BVds-off by 30% because of the reduction of gate leakage current. It also improved ηd in the output power characteristics by load-pull measurement, which indicates the decrease of the current collapse phenomenon. Also we fabricated a multi-fingered 50 W-class AlGaN/GaN HEMT with T-CVD SiN passivation film and achieved 61.2% of high drain efficiency at frequency of 2.14 GHz, which was 3.6 points higher than that with PE-CVD SiN passivation film.

In AlGaN/GaN high electron mobility transistors (HEMTs), drain current reduction by current collapse phenomenon is a big obstacle for a high efficient operation of power amplifier application. In this study, we investigated the effects of SiN passivation film quality on the electrical characteristics of AlGaN/GaN HEMTs. First, we conducted some experiments to investigate the relationship between electrical characteristics of AlGaN/GaN HEMTs and various conditions of SiN passivation film by plasma enhanced chemical vapor deposition (PE-CVD). We found that both gate current leakage and current collapse were improved simultaneously by SiN passivation film deposited by optimized condition of NH3 and SiH4 gas flow. It is found that the critical parameter in the optimization is a IN-H/ ISi-H ratio measured by Fourier transforms infrared spectroscopy (FT-IR) spectra. Next, a thermal CVD SiN was applied to the passivation film to be investigated from the same point of view, because a thermal CVD SiN is well known to have good quality with low hydrogen content and high IN-H/ISi-H ratio. We confirmed that the thermal CVD SiN passivation could improve much further both of the gate leakage current and the current collapse in AlGaN/GaN-HEMTs. Furthermore, we tried to apply the thermal CVD SiN to the gate insulator in MIS (Metal Insulator Semiconductor) structure of AlGaN/GaN HEMTs. The thermal CVD SiN passivation was more suitable for the gate insulator than PE-CVD SiN passivation in a view of reducing current collapse phenomena. It could be believed that the thermal CVD SiN film is superior to the PE-CVD SiN film to achieve good passivation and gate insulator film for AlGaN/GaN HEMTs due to the low hydrogen content and the high IN-H/ISi-H ratio.

Heterostructure field-effect transistors (HFETs) composed of antimonide-based compound semiconductor (ABCS) materials have intrinsic performance advantages due to the attractive electron and hole transport properties, narrow bandgaps, low ohmic contact resistances, and unique band-lineup design flexibility within this material system. These advantages can be particularly exploited in applications where high-speed operation and low-power consumption are essential. In this paper, we report on recent advances in the design, material growth, device characteristics, oxidation stability, and MMIC performance of Sb-based HEMTs with an InAlSb upper barrier layer. The high electron mobility transistors (HEMTs) exhibit a transconductance of 1.3 S/mm at VDS = 0.2 V and an fTLg product of 33 GHz-µm for a 0.2 µm gate length. The design, fabrication and improved performance of InAlSb/InGaSb p-channel HFETs are also presented. The HFETs exhibit a mobility of 1500 cm2/V-sec, an fmax of 34 GHz for a 0.2 µm gate length, a threshold voltage of 90 mV, and a subthreshold slope of 106 mV/dec at VDS = -1.0 V.

Capless high electron mobility transistors (HEMTs) were fabricated and their DC and RF performances were characterized. Capless HEMTs did not have highly doped InGaAs cap layer so that gate recess process was not required in the fabrication of capless HEMTs. The electrical performances of the capless HEMTs were compared with those of conventional HEMTs with highly doped InGaAs cap layer. A typical 0.2 µm capless HEMT exhibited a maximum transconductance of 805 mS/mm, a threshold voltage of -0.5 V, and a unity current gain cut-off frequency (fT) of 137 GHz. Capless HEMTs exhibited improved device uniformity compared with conventional HEMTs fabricated by wet gate recess technology.

In AlGaN/GaN high electron mobility transistors (HEMTs), Si3N4 passivation film brings effective improvements in the current collapse phenomenon, however, the suppression of this phenomenon in a high voltage operation can not be achieved in only the Si3N4 deposition process. In order to solve this problem, we have demonstrated an NH3-plasma surface pretreatment in the chamber of plasma enhanced chemical vapor deposition (PE-CVD) just before Si3N4 deposition process. We found that the optimized NH3-plasma pretreatment could improve the current collapse as compared with only the Si3N4 deposition and an excessive pretreatment made it worse adversely in AlGaN/GaN-HEMTs. It was confirmed by Auger electron spectroscopy (AES) analysis that the optimized NH3-plasma pretreatment decreased the carbon contamination such as hydrocarbon on the AlGaN surface and the excessive pretreatment degraded the stoicheiometric composition of AlGaN surface.

Recessed 0.15 µm gate-length AlGaN/GaN high electron mobility transistors (HEMTs) were fabricated using inductively-coupled-plasma reactive ion etching (ICP-RIE) on sapphire substrate. These 0.15 µm gate-length devices exhibited maximum drain current density as high as 1.4 A/mm and peak extrinsic transconductance of 346 mS/mm. The threshold voltage was -4.1 V. A unity gain cut-off frequency (fT) of 80 GHz and maximum frequency of oscillation (fmax) of 73 GHz were measured on these devices. Pulsed I-(V) measurements did not show any significant dispersion. At 20 GHz, a continuous-wave (CW) output power density of 3.1 W/mm with power-added-efficiency (PAE) of 29.9% was obtained.

A new method is proposed for determining the parasitic extrinsic resistances of MESFETs and HEMTs from the measured S-parameters under active bias. The proposed method is based on the fact that the difference between drain resistance (Rd) and source resistance (Rs) can be found from the measured S-parameters under zero bias condition. It is possible to define the new internal device including intrinsic device and three extrinsic resistances by eliminating the parasitic imaginary terms. Three resistances can be calculated easily via the presented explicit three equations, which are induced from the fact that 1) the real parts of Yint,11 and Yint,12 of intrinsic Y-parameters are very small or almost zero, 2) the transformation relations between S-, Z-, and Y-matrices. The modelled S-parameters calculated by the obtained resistances and all the other equivalent circuit parameters are in good agreement with the measured S-parameters up to 40 GHz.

A 50-Gbit/s demultiplexer IC module that uses 0.1-µm InAlAs/InGaAs/InP HEMTs is reported. The maximum error-free operation bit-rate of a fabricated module is 50 Gbit/s, and a wide phase margin of 170 degrees is obtained at 43 Gbit/s. 50-Gbit/s demultiplexing is the fastest performance of all packaged demultiplexer ICs yet reported.

An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.