Orientation field (OF) estimation is a fundamental process in fingerprint authentication systems. In this paper, a novel binary pattern based low-cost OF estimation algorithm is proposed. The new method consists of two modules. The first is block-level orientation estimation and averaging in vector space by pixel level orientation statistics. The second is orientation quantization and smoothing. In the second module, the continuous orientation is quantized into fixed orientations with sufficient resolution (interval between fixed orientations). An effective smoothing scheme on the quantized orientation space is also proposed. The proposed algorithm is capable of stably processing poor-quality fingerprint images and is validated by tests conducted on an adaptive OF matching scheme. The proposed algorithm is also implemented into a fingerprint System on Chip (SoC) to comfirm that it satisfies the strict requirements of embedded system.

This paper reports the effect of corpus size on case frame acquisition for predicate-argument structure analysis in Japanese. For this study, we collect a Japanese corpus consisting of up to 100 billion words, and construct case frames from corpora of six different sizes. Then, we apply these case frames to syntactic and case structure analysis, and zero anaphora resolution, in order to investigate the relationship between the corpus size for case frame acquisition and the performance of predicate-argument structure analysis. We obtained better analyses by using case frames constructed from larger corpora; the performance was not saturated even with a corpus size of 100 billion words.

A new estimation algorithm of clock drift in symbol duration for high precision ranging, based on multiple symbols of chirp spread spectrum (CSS) is proposed. Since the permissible error of a crystal oscillator in CSS is relatively high given the need to lower device costs, ranging results are perturbed by clock drift. We establish the phenomenon of clock drift in multiple symbols of CSS, and estimate the clock drift in symbol duration based on phase difference between adjacent symbols. The proposed algorithm is analyzed, and verified by Monte Carlo simulations.

This paper proposes a novel adaptive image interpolation method using an edge-directed smoothness filter. Adaptive image interpolation methods tend to create higher visual quality images than traditional interpolation methods such as bicubic interpolation. These methods, however, often suffer from high computational costs and production of inadequate interpolated pixels. We propose a novel method to overcome these problems. Our approach is to estimate the enlarged image from the original image based on an observation model. Obtaining an image with edge-directed smoothness, we constrain the estimated image to have many edge-directed smooth pixels which are measured by using the edge-directed smoothness filter introduced in this paper. Additionally, we also propose a simplification of our algorithm to run with lower computational complexity and smaller memory. Simulation results show that the proposal method produces images with high visual quality and performs well on PSNR and computational times.

Bag-of-Visual-Words representation has recently become popular for scene classification. However, learning the visual words in an unsupervised manner suffers from the problem when faced these patches with similar appearances corresponding to distinct semantic concepts. This paper proposes a novel supervised learning framework, which aims at taking full advantage of label information to address the problem. Specifically, the Gaussian Mixture Modeling (GMM) is firstly applied to obtain "semantic interpretation" of patches using scene labels. Each scene induces a probability density on the low-level visual features space, and patches are represented as vectors of posterior scene semantic concepts probabilities. And then the Information Bottleneck (IB) algorithm is introduce to cluster the patches into "visual words" via a supervised manner, from the perspective of semantic interpretations. Such operation can maximize the semantic information of the visual words. Once obtained the visual words, the appearing frequency of the corresponding visual words in a given image forms a histogram, which can be subsequently used in the scene categorization task via the Support Vector Machine (SVM) classifier. Experiments on a challenging dataset show that the proposed visual words better perform scene classification task than most existing methods.

The relationship between the degree of overlap in direct modulation chirp spread spectrum systems with binary phase shift keying and intersymbol interference (ISI) is analyzed. It is observed that the ISI due to overlap fluctuates or monotonically increases as the number of overlaps changes and that, in some cases, the overlap does not incur ISI at all.

In this paper, we study multi-layer transmission for wireless multimedia multicast in a cell. Under the assumptions that the users in a cell are uniformly well distributed and that the BS has no channel side information, we find the optimal number of transmission layers and power allocation. This result can be used in highly dynamic dense networks and jamming networks where channel side information at the transmitter is somewhat useless.

We present a technology based on Nb/NbxSi1-x/Nb junctions, with barriers near the metal-insulator transition, for applications in superconducting electronics (SCE) as an alternative to Nb/AlOx/Nb tunnel junctions. Josephson junctions with co-sputtered amorphous Nb-Si barriers can be made with a wide variety of electrical properties: critical current density (Jc), capacitance (C), and normal resistance (Rn) can be reliably selected within wide ranges by choosing both the barrier thickness and Nb concentration. Nonhysteretic Nb/NbxSi1-x/Nb junctions with IcRn products greater than 1 mV, where Ic is the critical current, and Jc values near 100 kA/cm2 have been fabricated and are promising for superconductive digital electronics. These barriers have thicknesses of several nanometers; this improves fabrication reproducibility and junction uniformity, both of which are necessary for complex digital circuits. Recent improvements to our deposition system have allowed us to obtain better uniformity across the wafer.

All MgB2 Josephson junctions with amorphous boron barriers have been fabricated on C-plane sapphire substrates by using a co-evaporation method. The junctions showed Josephson currents and the nonlinear current-voltage characteristics which seem to reflect the superconducting energy gap. The critical current was observed when the thickness of the amorphous boron was in the range of 5 nm to 20 nm. The critical current density was estimated to be 0.4 A/cm2 to 450 A/cm2. By observing he temperature dependence of the critical current we found that the junction had a critical temperature of 10 K and a normal layer in its barrier structure.

A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.

The usage of light-weight mobile devices is increasing rapidly, leading to demand for more telecommunication services. Consequently, mobile ad hoc networks and their applications have become feasible with the proliferation of light-weight mobile devices. Many protocols have been developed to handle service discovery and routing in ad hoc networks. However, the majority of them did not consider one critical aspect of this type of network, which is the limited of available energy in each node. Cluster Based Routing Protocol (CBRP) is a robust/scalable routing protocol for Mobile Ad hoc Networks (MANETs) and superior to existing protocols such as Ad hoc On-demand Distance Vector (AODV) in terms of throughput and overhead. Therefore, based on this strength, methods to increase the efficiency of energy usage are incorporated into CBRP in this work. In order to increase the stability (in term of life-time) of the network and to decrease the energy consumption of inter-cluster gateway nodes, an Enhanced Gateway Cluster Based Routing Protocol (EGCBRP) is proposed. Three methods have been introduced by EGCBRP as enhancements to the CBRP: improving the election of cluster Heads (CHs) in CBRP which is based on the maximum available energy level, implementing load balancing for inter-cluster traffic using multiple gateways, and implementing sleep state for gateway nodes to further save the energy. Furthermore, we propose an Energy Efficient Cluster Based Routing Protocol (EECBRP) which extends the EGCBRP sleep state concept into all idle member nodes, excluding the active nodes in all clusters. The experiment results show that the EGCBRP decreases the overall energy consumption of the gateway nodes up to 10% and the EECBRP reduces the energy consumption of the member nodes up to 60%, both of which in turn contribute to stabilizing the network.

This paper proposes an efficient fingerprint recognition algorithm combining phase-based image matching and feature-based matching. In our previous work, we have already proposed an efficient fingerprint recognition algorithm using Phase-Only Correlation (POC), and developed commercial fingerprint verification units for access control applications. The use of Fourier phase information of fingerprint images makes it possible to achieve robust recognition for weakly impressed, low-quality fingerprint images. This paper presents an idea of improving the performance of POC-based fingerprint matching by combining it with feature-based matching, where feature-based matching is introduced in order to improve recognition efficiency for images with nonlinear distortion. Experimental evaluation using two different types of fingerprint image databases demonstrates efficient recognition performance of the combination of the POC-based algorithm and the feature-based algorithm.

This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by static fluctuation and dynamic fluctuation due to temperature and supply voltage changes. The ADC has been fabricated in 90-nm 1P10M CMOS technology. Experimental results show that the ADC achieves SNDR of 6.07 bits without calibration and 6.74 bits with calibration up to 500 MHz input signal at sampling rate of 600 MSps. It dissipates 98.5 mW on 1.2-V supply. FoM is 1.54 pJ/conv.

Digital fingerprinting is used to trace back illegal users, where unique ID known as digital fingerprints is embedded into a content before distribution. On the generation of such fingerprints, one of the important properties is collusion-resistance. Binary codes for fingerprinting with a code length of theoretically minimum order were proposed by Tardos, and the related works mainly focused on the reduction of the code length were presented. In this paper, we present a concrete and systematic construction of the Tardos's fingerprinting code using a chaotic map. Using a statistical model for correlation scores, the actual number of true-positive and false-positive detection is measured. The collusion-resistance of the generated fingerprinting codes is evaluated by a computer simulation.

Partial plasma polymerization for coexistence of hydrophobic/hydrophilic area in several ten micrometer size is the typical technique for protein patterning. A hydrophobic hexamethyldisiloxane plasma-polymerized film (HMDS PPF) was deposited on a glass substrate and this surface was partially modified by subsequent nitrogen plasma treatment (hydrophilic surface, HMDS-N PPF) with a patterned shadow mask. An antibody protein (F(ab')2 fragment of anti-human immunoglobulin G) was selectively adsorbed onto the HMDS-N area and was not adsorbed onto the HMDS area. Distinct 8080 µm2 square spots surrounded by a non-protein adsorbed 80 µm-wide grid were observed. Then, when the protein modified by fullerene was used, the reversible patterning was obtained. This indicated that the modification by fullerene changed the hydrophilic nature of F(ab')2 protein to hydrophobic one, as a result, the modified protein was selectively adsorbed onto hydrophobic area.

In 3D IC design, thermal issue is a critical challenge. To eliminate hotspots, physical layouts are always adjusted by some incremental changes, such as shifting or duplicating hot blocks. In this paper, we distinguish the thermal-aware incremental changes in three different categories: migrating computation, growing unit and moving hotspot blocks. However, these modifications may degrade the packing area as well as interconnect distribution greatly. In this paper, mixed integer linear programming (MILP) models are devised according to these different incremental changes so that multiple objectives can be optimized simultaneously. Furthermore, to avoid random incremental modification, which may be inefficient and need long runtime to converge, here potential gain is modeled for each candidate incremental change. Based on the potential gain, a novel thermal optimization flow to intelligently choose the best incremental operation is presented. Experimental results show that migrating computation, growing unit and moving hotspot can reduce max on-chip temperature by 7%, 13% and 15% respectively on MCNC/GSRC benchmarks. Still, experimental results also show that the thermal optimization flow can reduce max on-chip temperature by 14% to the initial packings generated by an existing 3D floorplanning tool CBA, and achieve better area and total wirelength improvement than individual operations do. The results with the initial packings from CBA_T (Thermal-aware CBA floorplanner) show that 13.5% temperature reduction can be obtained by our incremental optimization flow.

As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. Distributed-register architectures can reduce the influence of interconnection delay. They may, however, increase circuit area because they require many local registers. Moreover original distributed-register architectures do not consider control signal delay, which may be the bottleneck in a circuit. In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Our method is based on iterative improvement of scheduling/binding and floorplanning. First, we prepare shared-register groups with global controllers, each of which corresponds to a single functional unit. As iterations proceed, we use local registers and local controllers for functional units on a critical path. Shared-register groups physically located close to each other are merged into a single group. Accordingly, global controllers are merged. Finally, our method obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 4.7% while maintaining the performance of the circuit equal with that using original distributed-register architectures.

Carbon nanofibers (CNFs) were fabricated on graphite plates using "Ar+ ion sputtering method" in large amount at room temperature. The morphology of CNFs was controlled by a simultaneous carbon supply during ion sputtering. CNF-tipped cones were formed on graphite plate surfaces without carbon supply whereas those with a simultaneous carbon supply featured mainly needle-like protrusions of large size. The field electron emission (FE) properties, measured using parallel plate configurations in 10-4 Pa range, showed the threshold fields of 4.4 and 5.2 V/µm with a current density of 1 µA/cm2 for CNF-tipped cones and needle-like protrusion, respectively. Reliability test results indicated that CNF-tipped cones were more stable than needle-like protrusion. The morphological change after reliability test showed a so-called "self-regenerative" process and structure damage for CNF-tipped cones and needle-like protrusions, respectively.

A three-dimensional semiconductor package structure with inter-chip connections was developed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a 10 µm scale fine-wiring pattern and ultra-fine-pitch through vias. This technology features co-existence of the wide-band memory accessibility of a system-on-chip (SoC) and the capability of memory capacity increasing of a system-in-package (SiP) that is made possible by the individual fabrication of memory and logic on independent chips. This technology can improve performance due to memory band widening and a reduction in the power consumed in inter-chip communications. This paper describes the concept, structure, process, and experimental results of prototypes of this package, called SMAFTI (SMAart chip connection with FeedThrough Interposer). This paper also reports the results of the fundamental reliability test of this novel inter-chip connection structure and board-level interconnectivity tests.

This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.