This is a survey of algorithmic results in the theory of "discrete convex analysis" for integer-valued functions defined on integer lattice points. The theory parallels the ordinary convex analysis, covering discrete analogues of the fundamental concepts such as conjugacy, the Fenchel min-max duality, and separation theorems. The technical development is based on matroid-theoretic concepts, in particular, submodular functions and exchange axioms.

This paper describes a nonblind digital beamformer for SDMA (space division multiple access) systems used when channels are power-limited. An array antenna with many elements is usually required to obtain high antenna gain for the reception of a low-level desired signal and the degree of freedom for the spatial discrimination of many users using the same frequency. The proposed beamformer is designed for such array antennas by employing the combination of a multibeam former and a maximal-ratio-combining (MRC) technique. The MRC technique is extended to a nonblind combiner that uses a training sequence contained in the desired signal. Basic analysis and numerical simulations of its performance, under the power-limited condition and with fixed user terminals, show that the speed and robustness of desired-signal acquisition and undesired-signal suppression may outperform recursive-least-squares (RLS) beamformer with less computation, when it is applied to an array antenna with many elements.

The proliferation and development of cellular voice systems over the past several years has exposed the capabilities and the effectiveness of wireless communications and, thus, has paved the way for wide-area wireless data applications as well. The demand for such applications is currently experiencing a significant increase and, therefore, there is a strong call for advanced and efficient mobile data technologies. This article deals with these mobile data technologies and aims to exhibit their potential. It provides a thorough survey of the most important mobile packet data services and technologies, including MOBITEX, CDPD, ARDIS, and the emerging GPRS. For each technology, the article outlines its main technical characteristics, discusses its architectural aspects, and explains the medium access protocol, the services provided, and the mobile routing scheme.

This paper summarizes power reduction methods applicable for VLSI bus systems in terms of reduction of signal swing, effective capacitance reduction and reduction of signal transition, which have been studied in authors' research group. In each method the basic concept is reviewed quickly along with some examples of its application. A future perspective is also described in conclusion.

This paper describes a new design method for multiply-adders able to process a large quantity of multimedia data. I propose a (signed digits)(unsigned digits) fixed-point multiply-add/subtract unit. The unit eliminates the problems caused by the critical one-bit arithmetic precision drop-off peculiar to the conventional (signed digits)(signed digits) fixed-point multiply scheme. By simultaneously counting in the carry-save form, based on 7-3 counters simultaneously inputting the accumulation terms and the add/sub operation terms of multiplication results, carries are propagated faster than in the conventional method.

Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such as bulk-driven, floating-gate, and self-cascode MOSFETs; (iv) basic LV building blocks; (v) multi-stage frequency compensation topologies; and (vi) fully-differential and fully-balanced systems.

20-Gbit/s multiplexer (MUX) and demultiplexer (DEMUX) ICs are successfully fabricated using production-level high-performance super-self-aligned silicon bipolar transistors (HSSTs) with a unity current gain cutoff frequency of 50 GHz and a maximum oscillation frequency of 65 GHz.

This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical simulation, the necessary precision is estimated to be 5 bits. We propose a nonlinear oscillator network circuit using the pulse modulation approach suitable for an analog-digital merged circuit architecture. The basic operations of the nonlinear oscillator circuit and the connection weight circuit are confirmed by SPICE circuit simulation. The circuit simulation results also demonstrate that image segmentation can be performed within the order of 100 µs.

A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

In order to investigate the possibility of avatar communication using sign-language, in this paper, we develop a sign-language chatting system on the Internet using CG aniamtion techniques between Korea and Japan. We construct the system in server-client architecture, where images of Korean or Japanese sign-language are analyzed into a series of parameters for sign-language animation by server. We transmit the parameters, which are text data instead of images or their compression, to clients and regenerate the corresponding CG animation using the received data. The chatting system is implemented with Visual C++ 5.0 on Windows platforms. Experimental results show that the sign-language could be used as a communication means between avatars of different languages.

The design of effective traffic and resource management policies is a key issue in the deployment of ATM-satellite systems. This paper proposes a technique of call admission control and dynamic resource management to support ATM traffic classes in satellite environments. The effectiveness of the strategy is assessed by referring to the EuroSkyWay multimedia satellite platform, based on Ka-band payload and on-board processing. The main advantage is the effective exploitation of the satellite bandwidth by means of the statistical multiplexing of traffic sources and the guarantee of QoS provisioning to both real-time and non real-time, constant and variable bit rate sources.

This paper proposes an improved nonlinear FET model along with its parameter extraction procedure suitable for the accurate prediction of inter-modulation product's levels (IM) and spurious responses in active and passive applications. This new model allows accurate capture of the drain current behavior and its derivatives with respect to the gate voltage and the drain voltage in the both the saturated and linear regions of the I-V biasing domain. It was found that this model accurately predicts the bias-dependent S-parameters as well as IM's levels for both amplifier and mixer applications up to mm-wave frequencies.

We compare between four Connection Admission Control schemes that use either the Gaussian or the Effective Bandwidth model with and without real-time traffic measurements. We demonstrate that under heavy multiplexing, the Gaussian is more efficient than the Effective Bandwidth approach in either case.

This paper describes the effect of lowering the supply voltage and threshold voltages on the energy reduction of an ultralow-voltage multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuit. The energy dissipation is evaluated using a graph with equispeed and equienergy lines on a supply voltage and a threshold voltage plane. In order to draw equispeed and equienergy lines for ultralow-voltage circuits, we propose a modified energy-evaluation model taking into account a input-waveform transition-time of the circuits. The validity of the proposed energy-evaluation model is confirmed by the evaluation of a gate-chain TEG and a 16-bit CLA adder fabricated with 0.25-µm MTCMOS/SIMOX technology. Using the modified model, the energy-reduction effect in lowering the supply voltage is evaluated for a single-Vth fully-depleted CMOS/SOI circuit, a dual-Vth CMOS circuit consisting of fully-depleted low- and medium-Vth MOSFETs, and a triple-Vth MTCMOS/SIMOX circuit. The evaluation reveals that lowering the supply voltage of the MTCMOS/SIMOX circuit to 0.5 V is advantageous for the energy reduction at a constant operating speed.

We introduce a new wavelet image coding framework using context-based zerotree quantization, where an unique and efficient method for optimization of zerotree quantization is proposed. Because of the localization properties of wavelets, when a wavelet coefficient is to be quantized, the best quantizer is expected to be designed to match the statistics of the wavelet coefficients in its neighborhood, that is, the quantizer should be adaptive both in space and frequency domain. Previous image coders tended to design quantizers in a band or a class level, which limited their performances as it is difficult for the localization properties of wavelets to be exploited. Contrasting with previous coders, we propose to trace the localization properties with the combination of the tree-structured wavelet representations and adaptive models which are spatial-varying according to the local statistics. In the paper, we describe the proposed coding algorithm, where the spatial-varying models are estimated from the quantized causal neighborhoods and the zerotree pruning is based on the Lagrangian cost that can be evaluated from the statistics nearby the tree. In this way, optimization of zerotree quantization is no longer a joint optimization problem as in SFQ. Simulation results demonstrate that the coding performance is competitive, and sometimes is superior to the best results of zerotree-based coding reported in SFQ.

Low Power design has emerged as a both practically and theoretically attractive theme in modern LSI system design. This paper presents system level power optimization techniques. A brief survey of system level low power design approaches and several examples in detail are described. It reviews some techniques that have been proposed to overcome the power issue and gives guideline for prospective system level solutions.

A new phasor model of neural networks is proposed in which the state of each neuron possibly takes the value at the origin as well as on the unit circle. A stability property of equilibria is studied in association with the energy landscape. It is shown that a simple condition guarantees an equilibrium to be asymptotically stable.

A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.

An analog standard cell layout configuration is proposed for simplifying the design and reducing the man-hours for designing mixed analog-digital LSIs, and analog standard cells are fabricated for A-D and D-A converters with Δ-Σ modulators. This works seeks to implement 2-D cell placement with up-down and left-right mirror rotation and shorter high-impedance analog wiring than conventional 1-D placement in order to obtain high-performance analog characteristics. By considering sensitivity to noise, routing channels have been classified into 4 types: high-impedance analog, low-impedance analog, analog-digital, and digital, and efforts have been made to prevent analog wires from crossing over digital wires. In addition to power and analog ground wires, analog standard cells have built-in analog ground wires with attached wells optimized for shielding. These wires are interconnected to a new isolation cell that separates analog circuits from digital circuits and routing channels. Based on the above layout structure, 46 different types of analog standard cells have been designed. Also, the analog part of Δ-Σ type A-D and D-A converters can be automatically designed in conjunction with interactive processing and chips fabricated by using these cells. It was found that, compared to manual design, one could easily obtain a chip occupying less than 1.5-times the area with about 2/3 the man-days using this approach. In comparison with manual design, it was also found that the S/N ratio could be reduced from about 6 to 7 dB.

A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.