In this paper, we present the theoretical development to stabilize a class of uncertain time-delay system. The system under consideration is described in state space model containing distributed delay, uncertain parameters and disturbance. The main idea is to transform the system state into an equivalent one, which is easier to analyze its behavior and stability. Then, a computational method of robust controller design is presented in two parts. The first part is based on solving a Riccati equation arising in the optimal control theory. In the second part, the finite dimensional Lyapunov min-max approach is employed to cope with the uncertainties. Finally, we show how the resulting control law ensures asymptotic stability of the overall system.

Feature selection is an integral part of any pattern recognition system. Removal of redundant features improves the efficiency of a classifier as well as cut down the cost of future feature extraction. Recently neural network classifiers have become extremely popular compared to their counterparts from statistical theory. Some works on the use of artificial neural network as a feature selector have already been reported. In this work a simple feature selection algorithm has been proposed in which a fractal neural network, a modified version of multilayer perceptron, has been used as a feature selector. Experiments have been done with IRIS and SONAR data set by simulation. Results suggest that the algorithm with the fractal network architecture works well for removal of redundant informations as tested by classification rate. The fractal neural network takes lesser training time than the conventional multilayer perceptron for its lower connectivity while its performance is comparable to the multilayer perceptron. The ease of hardware implementation is also an attractive point in designing feature selector with fractal neural network.

The aim of this contribution is to take a further step in the study of the impact of chaos-based techniques on classical DS-CDMA systems. The problem addressed here is the sequence phase acquisition and tracking which is needed to synchronize the spreading and despreading sequences of each link. An acquisition mechanism is considered and analyzed in depth to identify analytical expressions of suitable system performance parameters, namely outage probability, link startup delay and expected time to service. Special chaotic maps are considered to show that the choice of spreading sequences can be optimized to accelerate and improve the spreading codes acquisition phase.

A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.

An ultra-fast optoelectronic decision circuit using resonant tunneling diodes (RTD's) and a uni-traveling-carrier photodiode (UTC-PD) is proposed. The circuit employs two cascaded RTD's for ultra-fast logic operation and one UTC-PD that offers a direct optical input interface. This novel configuration is suitable for ultra-fast decision operation. Two types of decision circuits are introduced: a positive-logic type and a negative-logic type. Operations of these circuits were simulated using SPICE with precisely investigated RTD and UTC-PD models. In terms of circuit speed, 40-Gbit/s decision and 80-Gbit/s demultiplexing were expected. Furthermore, the superiority of the negative-logic type in terms of the circuit operating margin and the relationship between input peak photocurrent and effective logic swing were clarified by SPICE simulations. In order to confirm the basic functions of the circuits and the accuracy of the simulations, circuits were fabricated by monolithically integrating InP-based RTD's and UTC-PD's. The circuits successfully exhibited 40-Gbit/s decision operation and 80-Gbit/s demultiplexing operation with less than 10-mW power dissipation. The superiority of the negative-logic type circuit for the circuit operation was confirmed, and the relationship between the input peak photocurrent and the effective logic swing was as predicted.

A new hardware algorithm for the block matching video motion estimation is presented. The algorithm works in the full-search fashion but unlike the Full-Search Block Matching Algorithm (FSBMA) it adjusts the number of computations dynamically to variable picture contents. Due to incorporated mechanism of data-driven thresholding, the proposed algorithm performs as four times as less operations comparing to the FSBMA while maintaining the same quality of results. Its hardware implementation is simple and compact. A supportive hardware design as well as simulation results on benchmarks are outlined.

This paper gives a detailed presentation of a "vision chip" for a very fast detection of motion vectors. The chip's design consists of a parallel pixel array and column parallel block-matching processors. Each pixel of the pixel array contains a photo detector, an edge detector and 4 bits of memory. In the detection of motion vectors, first, the gray level image is binarized by the edge detector and subsequently the binary edge data is used in the block matching processor. The block-matching takes place locally in pixel and globally in column. The chip can create a dense field of motion where a vector is assigned to each pixel by overlapping 2 2 target blocks. A prototype with 16 16 pixels and four block-matching processors has been designed and implemented. Preliminary results obtained by the prototype are shown.

High-speed collision detection is important to realize a highly-safe intelligent vehicle. In collision detection, high-computational power is required to perform matching operation between discrete points on surfaces of a vehicle and obstacles in real-world environment. To achieve the highest performance, a hierarchical matching scheme is proposed based on two representations: the coarse representation and the fine representation. A vehicle is represented as a set of rectangular solids in the fine representation (fine rectangular solids), and the coarse representation, which is also a set of rectangular solids, is produced by enlarging the fine representation. If collision occurs between an obstacle discrete point and a rectangular solid in the coarse representation (coarse rectangular solid), then it is sufficient to check the only fine rectangular solids contained in the coarse one. Consequently, checks for the other fine rectangular solids can be omitted. To perform the hierarchical matching operation in parallel, a hierarchically-content-addressable memory (HCAM) is proposed. Since there is no need to perform matching operation in parallel with fine rectangular solids contained in different coarse ones, the fine ones are mapped onto a matching unit. As a result, the number of matching units can be reduced without decreasing the performance. Under the condition of the same execution time, the area of the HCAM is reduced to 46.4% in comparison with that of the conventional CAM in which the hierarchical matching scheme is not used.

This paper presents a new number representation called the Signed-Weight (SW) number system, which is useful for designing configurable counter-tree architectures for digital signal processing applications. The SW number system allows the unified manipulation of positive and negative numbers in arithmetic circuits by adjusting the signs assigned to individual digit positions. This makes possible the construction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as negation and sign extension in the two's complement representation. This paper also presents the design of a Field-Programmable Digital Filter (FPDF) architecture--a special-purpose FPGA architecture for high-speed FIR filtering--using the proposed SW arithmetic system.

Current computing systems are too slow for information processing because of the huge number of procedural steps required. A decrease in the number of calculation steps is essential for real-time information processing. We have developed two kinds of novel architectures for automatic elimination of redundant calculation steps. The first architecture employs the new digit-serial algorithm which eliminates redundant lower digit calculations according to the most-significant-digit-first (MSD-first) digit-serial calculation scheme. Basic components based on this architecture, which employ the redundant number system to limit carry propagation, have been developed. The MSD-first sequential vector quantization processor (VQP) is 3.7 times faster than ordinary digital systems as the result of eliminating redundant lower-bit calculation. The second architecture realizes a decrease in the number of complex calculation steps by excluding useless data before executing the complex calculations according to the characterized value of the data. About 90% of Manhattan-distance (MD) calculations in VQP are excluded by estimating the MD from the average distance.

This paper presents a low-power video A/D conversion technique using features of moving pictures. Neighboring frames in typical video sequences and neighboring pixels in each video frame are highly correlated. This property is effectively used for the video A/D conversion to reduce the number of comparators and the resulting power consumption. A set of reference voltages is given to a comparator array so that the iterative A/D conversion converges in the logarithmic order of the prediction error. Simulation results using standard moving pictures showed that the average number of iterations for the A/D conversion is less than 3 for all the moving pictures tested. In the proposed 12 b A/D converter, the number of comparators can be reduced to about 1/5 compared with that of the two-step flash A/D converters, which are commonly used for video applications. The A/D converter is particularly useful for the integration to CMOS image sensors.

A 32-bit motor-drive-specific microcontroller chip was newly designed, implemented using a 0.8 µm double-metal CMOS process, and its feasibility was successfully tested by applying the fabricated microcontroller chip to a real AC induction motor drive system. The microcontroller chip includes a single-precision floating-point unit, peripheral devices for motor drive, and a memory controller as well as the SPARC V7 CPU. The pipeline scheme and the two-step multiplication method were used in the multiplier of floating-point unit for the best area and speed trade-off, using the standard cell library available for the design. The chip size is 12.7 12.8 mm2, the number of transistors is around 562,000, and the power consumption is 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz. Both a standard cell library and a full-custom layout were used in the implementation.

The fact that there exists a core sinusoidal oscillator at the heart of Saito's double-screw hysteresis chaotic oscillator is demonstrated. By applying Bruton's transformation to the active linear part of the circuit, which is shown to be a classical LC-R negative resistor sinusoidal oscillator, an inductorless realization based on a frequency-dependent negative resistor (FDNR) is obtained. The LC-R sinusoidal oscillator is replaced by an FDNR-R oscillator. Furthermore, we show that chaotic behaviour can be preserved when a simple minimum component 2R-2C sinusoidal oscillator is used. Two different realizations of the non-monotone current-controlled hysteresis resistor, one of which is completely passive, are investigated. Experimental results of selected circuits, PSpice and numerical simulations are included.

The concept of a schedulable region (SR) was introduced to characterize the capacity of a multiplexer and provide a separation between call-level and cell-level phenomena. In this paper, we present a framework and algorithm for real-time estimation of the schedulable region. A major problem associated with online estimation is that the objects of measurement are not fixed in the presence of call arrivals and departures. The invariance property is exploited to carry out measurements in the presence of call arrivals and departures. By virtue of it, the equivalent bandwidth could be defined on the condition of the number of each traffic class call in progress. Another important thing we consider here is that the search algorithm to estimate the effective bandwidth should be chosen depending on the arrival statistics and QOS constraints. The algorithms presented here have been implemented on an ATM switch.

The current-voltage characteristics of a single electron transistor (SET) in the resonant transport mode are investigated. In the future when SET devices are applied to integrated electronics, the quantum effect will seriously modify their characteristics in ultra-small geometry. The current will be dominated by the resonant transport through narrow energy levels in the dot. The simple case of a two-level system is analyzed and the transport mechanism is clarified. The transport property at low temperatures (higher than the Kondo temperature) in the low tunneling rate limit is discussed, and a current map where current values are classified in the gate bias-drain bias plane is provided. It was shown that the dynamic aspect of electron flow seriously influences the current value.

This paper proposes a novel universal line termination scheme for the ONUs (optical network units) of fiber-optic local access systems. Its main feature is that only low cost AD/DA converters for Hi-Fi audio are needed. Because audio AD/DA converters are insufficient for ISDN basic rate access (● 320kbaud) and cause waveform distortion, we develop a simple detection algorithm that does not use any equalizing filter. The algorithm can handle plural channels with one general purpose MPU (micro-processing unit). Based on this, a novel architecture for a fiber-optic local access system is presented that removes the MPUs from each optical network unit (ONU) and places them in the central office (CO). The proposed system yields a small, service-uniform ONU that supports a wide range of narrow-band services (POTS & ISDN) with no distinction. To realize this system at the lowest possible cost, a high-speed code division multiplexing (CDM) scheme with novel code word sets is developed.

A partial buffer sharing scheme is proposed as loss-priority control for a finite buffer with batch Poisson inputs under a whole batch acceptance rule. Customer and batch loss probabilities for high- and low-priority customers are derived under this batch acceptance rule using a supplementary variable method. A comparison of the partial buffer sharing scheme and a system without loss-priority control is made in terms of admissible offered load. Whole batch acceptance and partial batch acceptance rules are also compared in terms of admissible offered load.

This letter proposes an integrated approach to multimedia ATM network design. An optimization model that combines the physical layer design with the logical layer design is developed. A key feature of the model is that the objective to be maximized is a profit function. It includes more comprehensive cost functions for the physical and logical layers. A simple heuristic algorithm to solve the model is presented. It should be useful in practice for network designers and operators. Some numerical examples are given to illustrate the application of the model and the algorithm.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.

We developd a method of implementing a multiple-valued Hopfield network on electronic circuits by using single-electron circuit technology. The single-electron circuit shows quantized behavior in its operation because of the discrete tunnel transport of electrons. It can therefore be successfully used for implementing neuron operation of the multiple-valued Hopfield network. The authors developed a single-electron neuron circuit that can produce the staircase transfer function required for the multiple-valued neuron. A method for constructing a multiple-valued Hopfield network by combining the neuron circuits was also developed. A sample network was designed that solves an example of the quadratic integer-programming problem. And a computer simulation demonstrated that the sample network can converge to its optimal state that represents the correct solution to the problem.