As the telecommunications network provides a greater variety of services and more rapidly incorporates new technologies, it has become important to ensure modular functional growth of the network. As a part of the endeavor toward this goal, this paper discusses the functional architecture of a network, which defines the functional elements and the interfaces between them. Object-oriented paradigm is applied to develop this architecture. Because the objects which will be made in the software will become too numerous to manage, it is proposed to make a functional element out of a set of objects, grouped together on the basis of functional affinity, plus an interface object. A functional element communicates with other functional elements only via its interface object. The physical location of each functional element can be hidden from other functional elements by the support of distributed processing environment. To secure real-time performance, communications between functional elements are classified into two classes: direct and indirect communications. In order to examine technical feasibility an evaluate the various alternatives of functional architecture, and experimental system called EONS (Experimental Object-oriented Nodal System) was developed. The hardware equipment of EONS consists of a switching unit and workstations. The functional architecture implemented in the EONS is structured in two layers: hardware-independent, logical control layer and hardware-dependent, resource control layer. As an example of service application, universal personal telecommunication (UPT) service has been implemented.

In order to make the implementation of network components flexible and cost effective, it is required to use widely available technologies as the implementation platform. The distributed operating systems can be adopted as such a platform, because they allow to implement a network component using multiple computers connected through a local area network. In this paper, we focus on the Intelligent Network (IN) whose network components are modelled as Functional Entities (FEs), and describe an implementation method of FEs using distributed operating systems. Our method is summarized as follows: The remote procedure call (RPC) is used for the access transparent inter-process communication. The lightweight process mechanism is used for handling concurrent requests. CCF/SSF (Call Control Function/Service Control Function) and SDF (Service Data Function) are implemented as an SSF server and an SDF server, respectively. SCF (Service Control Function) is composed of a Service Dispatcher and a set of Service Executors. The Service Dispatcher accepts all the requests for IN call processing and dispatches them to appropriate Service Executors. Service Executors are created for the individual IN services and execute the service logics. SDF server and Service Executor may be replicated for load partitioning.This paper has also described the implementation of experimental system supporting "Freephone" service based on our method, and showed the performance evaluation of the experimental system in terms of the real-time and concurrent call processing of IN services. We used Mach and SUN OS as a platform for implementing the servers for FEs. The experimental system using four workstations shows that it can handle up to 170IN calls in one second with the additional response time of less than 200msec, which is small enough compared with the response time for the basic connection control. Those results prove that our method is feasible for implementing practical FEs.

The pursuit of higher availability has resulted in the development of fault tolerant systems for many industries. However, system characteristics that can be perceived by the customer have never been diagnosed quantitatively. This paper considers the application of stochastic Petri nets with general firing times to modeling of a fault tolerant system and the use of discrete-event simulation methods for stochastic Petri nets to study the behavior of the system. The stochastic Petri net model incorporates factors that compose the system as well as those that accompany it, including RAS characteristics of products, personnel arrangements, and system management. By modeling the behavioral aspect of each factor, it is possible to diagnose a fault tolerant system quantitatively on the basis of customer impact.

Recent trends in down-sizing have resulted in the development of client server systems for many industries. This paper considers the application of stochastic Petri nets with general firing times for modeling of a concatenated client server system and the use of discrete-event simulation methods for stochastic Petri nets to study its behavior. This approach enables us to assess the most appropriate resource set of a concatenated client server system on the quantitative basis of the performability and the occurrence of system down conditions. Thus, system consultation, a new application of stochastic Petri nets, is presented.

The detection problem of fluctuating radar targets in the presence of interference (noise and clutter) is considered; the assumed model for both target and clutter is a zero-mean stationary Gaussian random process with assigned power spectral densities. The pertaing optimum linear processor, namely the Optimized Filtering, is derived and its performance are evaluated in different operating conditions, including mismatching with the designed model. Finally, comparison with filtering techniques designed for targets with zero spectral width, i.e. the Moving Target Detector, are performed.

Isolation characteristics, which are important factors in designing GaAs ICs, are investigated focusing on leak current between circuit elements on a semi-insulating substrate and on the sidegating effect that results from leak current between MESFETs. We have found that the large leak current comes from the projecting edge, located outside the channel, of the gate electrode and that this leak current is the main cause of the sidegating effect. By taking into account quantitatively evaluated isolation characteristics, we can improve LSI design rules to reproducible and reliable operation.

Advances in semiconductor technology have made it possible to develop an experimental 1000 MIPS superscalar RISC processor. The high performance of this processor was obtained using architectural concepts such as multiple CPU configuration, superscalar microarchitecture, and high-speed device technology. This paper focuses on the novel features of this RISC processor, its device technology, architectural characteristics and one technology that has been devised to make its integer CPU cores fault-tolerant.

This paper describes a new method for designing switching software called DDL (Data Driven Logic). The new design method adopts the dataflow concept and graphical programming using a dataflow diagram. A dataflow diagram is used for software representation, and a dataflow mechanism is emulated on a conventional von Neumann processor. The DDL method has the following advantages; (1) general advantages of dataflow software; i.e. easily understandable programs using graphical representations, and easy description of parallelism, (2) modular design using reusable software components, (3) easy design and programming with a graphical user interface. This paper presents the general concepts and structure of DDL. It also discusses the dataflow emulation mechanism, the DDL software development process, the DDL programming environment, an evaluation of the DDL call processing program applied to a commercial PABX, and some unsolved problems of DDL.

In most of the methods proposed so far to design approximately linear phase IIR digital filters (IIR DFs), the design takes place only in the time or in the frequency domain. However, when both magnitude and phase responses are considered, IIR DFs with better frequency responses can be obtained if their characteristics in both domains are taken into account. This paper proposes a design method for approximately linear phase IIR DFs, which is based on parameter estimation techniques in the time domain followed by a nonlinear optimization algorithm in the frequency domain. Several examples are presented, illustrating the proposed method.

This paper proposes a test case generation method for testing concurrent programs as a black box. Typical applications are system testing for switching systems and inter-operability testing for OSI products. We adopt a two-step approach: first generate the control flow graph which represents global behaviors of a given concurrent program, and then apply conventional test case generation methods for the control flow graph. To generate a control flow graph without state space explosion, the black-box equivalence between system behaviors is introduced. The proposed algorithm generates a minimal control flow graph which consists of representatives of equivalence classes. Two practical techniques for the second step are discussed for a case study using a commercial digital PBX. The results show the feasibility of the proposed method.

The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. With the delay time of logic elements such as TTL SN7400, the minimum delay time (dm), the maximum delay time (dM), and the typical delay time are specified in the manual, and the delay time of an element is one in the interval between dm and dM. Here we assume a discrete time, and we manipulate the variance of the delay time as a set of output strings corresponding to each delay time. We call the model as the combined delay model. Since many output strings are generated with a single input string, the usual timing simulation method cannot be applied. We propose a timing verification method using a behavior extraction method of logic circuits with respect to a time string set: with respect to the specified input set, the method extracts the output string set of each element in the circuit. We devised (1) a mechanism to keep the correspondence between a primary input string and an output string with respect to the primary input string, (2) a mechanism to manipulate the nondeterminism included in the combined delay model, and (3) an event-driven like data compaction method in representing finite automata. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuit with 100 elements or so. The method includes the state explosion, but the data compaction method and the extraction for only the specified input set are useful to control the state explosion.

Public switching systems are intensively realtime and multi-processing, very large, long-lived, and frequently modified. Programs that control switching systems are therefore required not only to have run-time efficiency but also to be easy to maintain and extend. This paper proposes a Concurrent Object Model and an Object-Oriented Switching Program Structure. The Concurrent Object Model ensures simple and efficient real-time multi-processing. This model allows logical switching components to be implemented as "objects" in software, and the structure of the program coincides with the structure of the logical model. The program structure proposed here uses distributed call processing, which allows building-block-structured switching systems. A prototype switching program proved the effectiveness of this approach and showed that the static and dynamic overheads are within the capacity of present VLSI technology.

To develop highly reliable switching software efficiently, a more powerful computer-aided verification system is needed. In this paper, we present an object-oriented switching software verification system, focusing on the basic concept and verification method. The system consists of three basic functions: a model of the switching system, a simulation control mechanism, and a verification mechanism. We also give our evaluation of this system.

We have successfully developed an optical receiver and a laser driver circuit which were implemented with 0.35 µm GaAs JFETs (junction Field Effect Transistors). The 0.35 µm GaAs. JFET had the typical transconductance of 480 mS/mm with small drain conductance. An interdigit MSM (Metal Semiconductor Metal) -type photodetector and the JFETs were monolithically integrated on a GaAs substrate for the optical receiver. The fabricated optical receiver demonstrated Gb/s operation with a very low power consumption of 8.2 mW. The laser driver circuit operated at up to 4.0 Gb/s.

This paper presents a protocol verification method which verifies that the behaviors of a protocol meet requirements. In this method, a protocol specification is expressed as Extended Finite State Machines (EFSM's) that can handle variables, and requirements are expressed using a branching-time temporal logic for a concise and unambiguous description. Using the acyclic expansion algorithm extended such that it can deal with EFSM's, the verification method first generates a state transition graph consisting of executable transitions for each process. Then a branching-time temporal logic formula representing a requirement is evaluated on one of the generated graphs which is relevant to the requirement. An executable state transition graph for each process is much smaller than a global state transition graph which has been used in the conventional verification techniques to represent the behaviors of the whole protocol system consisting of all processes. The computation for generating the graphs is also reduced to much extent for a large complex protocol. As a result, the presented method achieves efficient verification for requirements regarding a state of a process, transmission and reception of messages by a process, varibales of a process and sequences that interact among processes. The validity of the method is illustrated in the paper by the verification of a path-updating protocol for requirements such as process state reachability or fair termination among processes.

This paper presents unique specification environments for LOTOS, which is one of FDTs (Formal Description Techniques) developed in ISO. We first discuss the large gap in terms of syntax and semantics between informal specifications at the early stage of specification design and formal specifications based on FDT such as LOTOS. This large gap has been bridged by human intelligent works thus far. In order to bridge the large gap, we have designed user-friendly specification environments for FDTs. The outlines of SEGL (Specification Environment for G-LOTOS), CBP (Concept-Based Programming environment) and MBP (Model-Based Programming environment) are described. The effectiveness of software development under such an environment is demonstrated using application examples from OSI and non-OSI protocols.

The preparation of magnetic semiconductor thick film (MST) by means of spray printing and application to a temperature/gas/essence sensor have been proposed. The MST pattern is composed of ferrite, ruthenium compound, carbon black, binder and solvent. After the mixed mgnetic semiconductor fluid is sprayed on a substrate, the sample is sintered at 750. The MST with thickness of 40 µm is printed on the substrate in various shapes such as a plate, a ring or a rod. The magnetic property of MST depends on temperature, and the electrical property responds to gas and natural/artificial fruit essence. Therefore, the multipore ceramic MST operates as a gas sensor with high sensitivity and high stability.

Air-bridge metal interconnection technology is used for upper level power supply line interconnections in GaAs LSI's to reduce the signal propagation delay time. This technology reduces both parasitic capacitance between the signal line and the power supply line, and propagation delay in the signal line to about 10% and about 50%, respectively, compared to conventional 3-level interconnections without air-bridges. Under standard load conditions (FI=FO=2, length of load line=2 mm), the air-bridge technique leads to gate propagation delays which are about 60% of those in conventional interconnections. We fabricated 2.1-k gate Gate Arrays and 4-kb SRAM's using the air-bridge structure to interconnect power supply lines. For a Gate Array with 0.7 µm gate Buried P-layer Lightly Doped Drain (BPLDD) FET's, the typical gate propagation delay under standard load conditions was about 110 ps with a dissipation power of 1.4 mW/gate. SRAM's with 05 µm gate BPLDD's had typical access time (tacc) of 1.5 ns with a dissipation power of 700 mW/chip.

A conflict detection support method for combining additional telecommunication services with existing services is proposed. In this method, telecommunication services are described by the STR (State Transition Rule) method which specifies a set of state transition rules. Though conflict detection in the past depended on manual analysis by the designer, with this method, conflict candidates are mechanically narrowed down and indicated to the designer. All conflicts between five actual telecommunication service descriptions are detected in an experiment using a system developed in line with the proposed method.

This paper presents a method for LSI implementation of a long-tap acoustic echo canceller algorithm using the residue number system (RNS) and the mixed-radix number system (MRS). It also presents a quantitative comparison of echo canceller architectures, one using the RNS and the other using the binary number system (BNS). In the RNS, addition, subtraction, and multiplication are executed quickly but scaling, overflow detection, and division are difficult. For this reason, no echo canceller using the RNS has been implemented. We therefore try to design an echo canceller architecture using the RNS and the NLMS algorithm. It is shown that the echo canceller algorithm can be effectively implemented using the RNS by introducing the MRS. The quantitative comparison of echo canceller architectures shows that a long-tap acoustic echo canceller can be implemented more effectively in terms of chip size and power dissipation by the architecture using the RNS.