The interface between laser-recrystallized Si and SiO2 is investigated by means of capacitance-voltage curve measurements. The recrystallization is performed by scanning cw Ar+ laser. The change in the C-V curves shows that the laser-recrystallization generates positive charge and the fast interface states at the Si-SiO2 interface, and creates n-type defects in recrystallized bulk silicon. Nominal interface charge increases linearly with a laser power. The increase in the charge is enhanced by fast laser-beam scanning velocity. The change in the C-V curve is suppressed, if a substrate is heated up to 450 during recrystallization. Complete recovery of the induced change in the C-V curves requires a subsequent furnace annealing at a temperature as high as 1100. These phenomena are explained by the generation of oxygen vacancy at the Si-SiO2 interface and quenched-in point defects in the recrystallized Si. The oxygen vacancy is produced by a reaction between the melted Si and SiO2. The quenched-in defects are produced during fast cooling of the melted Si.

Localized temperature distribution in silicon on insulator (SOI) structures with trench isolations is calculated using three-dimensional computer simulation. Temperature rise in SOI transistors is about three times higher than in conventional structure transistors because the thermal conductivity of SiO2 is very low. If there are voids in the SiO2 layers and trench isolations, temperature in the SOI transistors increases significantly. A simple model is proposed to calculate steady-state temperature rise in SOI transistors.

This paper describes two algorithms based on Boolean formulations aimed at solving scheduling, the main subtask of data path synthesis. Using the first algorithm, all possible scheduling solutions can be obtained under a time constraint, something that cannot be accomplished with other available systems. The second algorithm produces feasible solutions without increasing the complexity of the problem. The effectiveness of the algorithms is confirmed through experimental studies.

The static characteristics of GaInAs(P)/GaInAsP quantum well laser diodes (QW LDs), with graded-index separate-confinement-heterostructure (GRIN-SCH) grown by metalorganic chemical vapor deposition (MOCVD), have been investigated experimentally in terms of threshold current density, internal waveguide loss, differential quantum efficiency and light output power. Very low threshold current density of 410 A/cm2, high characteristic temperature of 113 K, low internal waveguide loss of 5 cm-1, high differential quantum efficiency of 82% and high light output power of 100 mW were obtained in 1.3 µm GRIN-SCH multiple quantum well (MQW) LDs by optimizing the quantum well structure including confinement layer and cavity design. Excellent uniformity for the threshold current, quantum efficiency and emission wavelength was obtained in all MOCVD grown buried heterostructure GRIN-SCH MQW LDs. Lasing characteristics of 1.5 µm GRIN-SCH MQW LDs are also described.

A vertex-capacitated network is a graph whose edges and vertices have infinite positive capacities and finite positive capacities, respectively. Such a network is a model of a communication system in which capacities of links are much larger than those of stations. This paper considers a problem of realizing a flow-saturation in an undirected vertex-capacitated network by adding the least number of edges. By defining a set of influenced vertex pairs by adding edges, we show the follwing results.(1) It suffices to add the least number of edges to unsaturated vertex pairs for realizing flow-saturation.(2) An associated graph of a flow-unsaturated network defined in this paper gives us a sufficient condition that flow-saturation is realized by adding a single edge.

The demand for mobile communications is continuing to grow, but there is a limit on the radio frequency resources. Micro cellular systems are a strong solution to this problem. However, Forced Call Termination (FCT) and Channel Changing (CC) occur frequently in these systems because of their small cell size. This paper proposes a new Dynamic Channel Assignment (DCA) strategy which uses information of moving direction of Mobile Stations (MSs) to reduce FCT and CC. This strategy, the MD (Moving Direction) strategy, is compared with other major DCA strategies by simulating a one-dimensional service area covering a road, such as an expressway. The simulation shows that the MD strategy performs better than the other strategies with regard to FCT, CC, and carried load. FCT is an especially important factor in the quality of service. The MD strategy reduces FCT and has the largest carried load of the strategies, which means that it has the most efficient channel usage. This is an attractive characteristic of the MD strategy for micro cellular systems.

Processors are important resources of stored program control (SPC) switching systems, and estimation of their workload level is crucial to maintaining service quality. Processor utilization is measured as processor usage per unit time, and workload level is usually estimated from measurement of this utilization during a given interval. This paper provides an approximate distribution of processor utilization of SPC switching systems, and it provides a method for designing an overload detection scheme. This method minimizes the observation interval required to keep overload detection errors below specified values. This observation interval is obtained as an optimal solution of a linear programming.

We fabricated a 4 GHz thin-base (120 nm) lateral bipolar transistor on bonded SOI by applying our sidewall self-aligning base process. By applying this device to BiCMOS circuits, bipolar transistor base junction capacitance, and MOSFET source and drain capacitance were very small. Furthermore, MOSFET and bipolar transistors are completely isolated from each other. Thus, it is easy to optimize MOS and bipolar processes, and provide protection from latch-up problems and soft errors caused by α-particles. In this paper, we describe device characteristics and discuss the crystal quality degradation introduced by ion implantation, and two dimensional effects of base diffusion capacitance.

The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.

Modeling and performance analysis have played an important role in the economical design and efficient operation of switching systems, and is currently becoming more important because the switching systems should handle a wide range of traffic characteristics, meeting the grade of service requirements of each traffic type. Without these techniques we could no longer achieve economy and efficiency of the switching systems in complex traffic characteristic environments. From the beginning of research on electronic switching systems offering circuit-switched applications, Stored Program Control (SPC) technology has posed challenges in the area of modeling and performance analysis as well as queueing structure, efficient scheduling, and overload control strategy design. Not only teletraffic engineers and performance analysts, but also queueing theorists have been attracted to this new field, and intensive research activities, both in theory and in practice, have continued over the past two decades, now evolving to even a broader technical field including traditional performance analysis. This article reviews a number of important issues that have been raised and solved, and whose solutions have been reflected in the design of SPC switching systems. It first discusses traffic problems for centralized control systems. It next discusses traffic problems inherent in distributed switching systems.

This paper describes a perspective on Personal Communicatoins Services (PCS) and technological trends. It takes into consideration rules pertaining to the use of PCS for mobile radio communication and countermeasures to cope with the huge increase in PCS subscribers. In this paper, PCS network structures, inter-regional roaming, microcell structure, radio access and channel access methods are also covered as PCS technologies. Furthermore, trends in domestic and international standards are also described. Although these technologies present many difficulties, we believe that they will be overcome and PCS services will be introduced in the near future.

Frequency Selective Screens (FSS) with conductor or complementary aperture array are investigated. The electric current distribution on conductor or the magnetic current distribution on aperture is determined by the moment method in the spectral domain. In addition, the power reflection coefficients are calculated and the scattering properties are considered.

This paper surveys the developments and achievements of teletraffic studies in Japan. It briefly covers the period preceding 1970, then focuses on the period after 1970. Rather than attempting to cover the entire field of teletraffic engineering, it places its emphasis on basic models.

This paper is a study on the behavioral aspects of the input buffer limiting scheme whose basic feature is to award priority to the transit messages over the input messages so that congestion does not develop in the network. The numerical method employed in the analysis is that proposed in Ref.(7). The performance aspects are studied for different buffer capacities, different message handling capacities and different levels of reservation for transit traffic. The numerical method indicates that thrashing occurs at low levels of reservation for the transit messages, irrespective of the buffer size or the processor capacities of the node. This observation is supported by simulation results. With reference to the state-space of the model of our study, the congestion aspects are related to two Liapunov functions. Under the domain of one of the Liapunov functions, the evolution of the perturbed system is towards a congested state whereas, under the domain of the other Liapunov function, the evolution is towards a congestion-free state. Regardless of the configuration, it is found that the fundamental characteristic of the congestion under the input buffer limiting scheme is the characteristic of a fold catastrophe. In the systems with insufficient level of reservation for the transit traffic, the performance degradation appears to be inevitable, irrespective of the capacities of the nodal processor and output channel processor, and the size of the buffer pool. Given such an inevitability, the active life of a node under a typical node configuration is studied by simulation. A suitable performance index is suggested to assess the performance of deadlock-prone nodes.

Rate based control is a promising way to achieve an efficient packet transmission especially in high speed packet switching networks where round trip delay is much larger than packet transmission time. Although inappropriate tuning for the parameters, increasing and decreasing factors, of the rate control function causes the performance degradation, most of the previous works so far have not studied the effect of the parameters on the performance. In this paper, we investigate the effect of the rate control parameters on the throughput under the condition that the packet loss probability is kept below a specific value, say 10-6. For this purpose, we build a queueing model and carry out a transient analysis to examine the dynamic behavior of the queue length at an intermediate node in a high speed network suffering from large propagation delay. Numerical examples exploit the optimal value of the parameters when one or two source-destination pairs transmit packets. We also discuss the effect of the propagation delay on the performance. Our model can be applicable to investigate the performance of various kinds of rate-based congestion control when the relation between the congestion measure and the rate control mechanism is given explicitly.

Video service is slated to be a major application of emerging high-speed communications networks of the future. In particular, full-motion video is designed to take advantage of the high bandwidths that will become affordably available with the advent of B-ISDN. A salient feature of compressed video sources is that they give rise to autocorrelated traffic streams, which are difficult to model with traditional modeling techniques. In this paper, we describe a new methodology, called TES (Transform-Expand-Sample) , for modeling general autocorrelated time series, and we apply it to traffic modeling of compressed video. The main characteristic of this methodology is that it can model an arbitrary marginal distribution and approximate the autocorrelation structure of an empirical sample such as traffic measurements. Furthermore, the empirical marginal (histogram) and leading autocorrelations are captured simultaneously. Practical TES modeling is computationally intensive and is effectively carried out with software support. A computerized modeling environment, called TEStool, is briefly reviewed. TEStool supports a heuristic search approach for fitting a TES model to empirical time series. Finally, we exemplify our approach by two examples of TES video source models, constructed from empirical codec bitrate measurements: one at the frame level and the other at the group-of-block level. The examples demonstrate the efficacy of the TES modeling methodology and the TEStool modeling environment.

A study of hot-carrier-induced photon emission in thin SOI/MOSFETs has been carried out both for bonded-SOI and SIMOX/SOI. The photon emission is observed not only in the drain region but also in the source region for SOI/MOSFETs, whereas only in the drain region for conventional bulk MOSFETs. From the emission spectrum, it can be concluded that the emission mechanism of the source region is probably a photon-assisted direct recombination of electrons and holes, while both the recombination and Bremsstrahlung are the possible mechanism for the drain region. The total photo intensity from SOI/MOSFETs increases as the SOI film thickness decreases, showing that strong impact ionization occurs near the drain region for thinner SOI devices. The relation between the lifetime and the photo intensity for SOI/MOSFETs is very similar to that between the lifetime and the substrate current for conventional bulk/MOSFETs, proving that photon emission is a good indicator of the hot carrier degradation in thin SOI/MOSFETs. The lifetime measurement using the photon emission both for SOI and bulk devices indicates that longer lifetime can be expected for thin film SOI/MOSFETs with a reduced drain bias which will be indispensable for future sub-half micron MOSFETs.

Strongly Fault-Secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly Code-Disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. This paper presents a new generalized design method for the SFS and SCD realization of combinational circuits. The proposed design is simple, and always gives an SFS and SCD combinational circuit which implements any given logic function. The resulting SFS/SCD circuits can be connected in cascade with each other to construct a larger SFS/SCD circuit if each interface is fully exercised.

This paper describes the derivation of a parallel program from a nondeterministic sequential program using a bottom-up parser as an example. The derivation procedure consists of two stages: exploitation of AND-parallelism and exploitation of OR-parallelism. An interpreter of the sequential parser BUP is first transformed so that processes for the nodes in a parsing tree can run in parallel. Then, the resultant program is transformed so that a nondeterministic search of a parsing tree can be done in parallel. The former stage is performed by hand-simulation, and the latter is accomplished by the compiler of ANDOR-, which is an AND/OR parallel logic programming language. The program finally derived, written in KL1 (Kernel Language of the FGCS Project), achieves an all-solution search without side effects. The program generated corresponds to an interpreter of PAX, a revised parallel version of BUP. This correspondence shows that the derivation method proposed in this paper is effective for creating efficient parallel programs.

In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, we aimed to create an unprecedentedly high software and hardware fault tolerance. We devised a fault tolerant architecture and various methodologies to ensure fault tolerance. We implemented these techniques systematically throughout operating system development. In the design stage, we developed a design methodology called the recovery process chart to verify that recovery mechanisms were complete. In the manufacturing stage, we applied the concept of critical routes to recovery and other processes essential to high dependability. We also developed a method of finding critical routes in a recovery process chart. In the test stage, we added an artificial software fault injection mechanism to the operating system. It generates various reproducible errors at appropriate times and reduces the number of personnel needed for test, making system reliability evaluation easy.