A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.

The subject of the paper is to propose an O(|V|+|E|) algorithm for the 3-edge-connectivity augmentation problem (UW-3-ECA) defined by "Given an undirected graph G0=(V,E), find an edge set E of minimum cardinality such that the graph (V,EE ) (denoted as G0+E ) is 3-edge-connected, where each edge of E connects distinct vertices of V." Such a set E is called a solution to the problem. Let UW-3-ECA(S) (UW-3-ECA(M), respectively) denote UW-3-ECA in which G0+E is required to be simple (G0+E may have multiple edges). Note that we can assume that G0 is simple in UW-3-ECA(S). UW-3-ECA(M) is divided into two subproblems (1) and (2) as follows: (1) finding all k-edge-connected components of a given graph for every k3, and (2) determining a minimum set of edges whose addition to G0 result in a 3-edge-connected graph. Concerning the subproblem (1), we use an O(|V|+|E|) algorithm that has already been existing. The paper proposes an O(|V|+|E|) algorithm for the subproblem (2). Combining these algorithms makes an O(|V|+|E|) algorithm for finding a solution to UW-3-ECA(M). Furthermore, it is shown that a solution E to UW-3-ECA(M) is also a solution to UW-3-ECA(S) if |V|4, partly solving an open problem UW-k-ECA(S) that is a generalization of UW-3-ECA(S).

A new technique for evaluating gate oxide reliability using photon emission method has been developed. This method enables the measurements of the initial breakdown characteristics, reliability testing and failure analysis consistently. From the experimental results, followings are clarified for the first time using this technique. Failure modes in the initial characteristics have close correlation to TDDB characteristics and both characteristics correspond to the location of breakdown spot. The results suggest measures to improve the reliability of gate oxide and the existance of new failure mechanism.

In this paper, we discuss secure protocols for shared computation of algorithms associated with digital signature schemes based on discrete logarithms. Generic solutions to the problem of cooperatively computing arbitraty functions, though formally provable according to strict security notions, are inefficient in terms of communication--bits and rounds of interaction--; practical protocols for shared computation of particular functions, on the other hand, are often shown secure according to weaker notions of security. We propose efficient secure protocols to share the generation of keys and signatures in the digital signature schemes introduced by Schnorr (1989) and ElGamal (1985). The protocols are built on a protocol for non-interactive verifiable secret sharing (Feldman, 1987) and a novel construction for non-interactively multiplying secretly shared values. Together with the non-interactive protocols for shared generation of RSA signatures introduced by Desmedt and Frankel (1991), the results presented here show that practical signature schemes can be efficiently shared.

The authors recently proposed a design method of stable IIR digital filters based on the interpolation by rational characteristic functions of filters, for a set of values of these characteristic function and, in addition, their higher derivatives prescribed at a number of frequency. This method can be further extended so that, despite usage of a less number of interpolation points, almost the same filter characteristics as one obtained by the former method can be realized. This paper presents an improved design method for making the transfer function meet strict magnitude specifications. The method proposed in this paper is especially efficient for designing a filter whose characteristics is specified not only in the passband but also in the transition band with relatively narrow bandwidth.

We propose a design method for a two-channel perfect reconstruction FIR filter banks employing linear-phase filters. This type of filter bank is especially important in splitting image signals into frequency bands for subband image cording. Because in such an application, it is necessary to use the combination of linear-phase filters and symmetric image signal, namely linear phase signal to avoid the increase in image size caused by filtering. In this paper, first we summarize the design conditions for two-channel filter banks. Next, we show that the design problem is reduced to a very simple linear equation, by using a half-band filter as a lowpass filter. Also the proposed method is available to lead filters with fewer complexity, which enable us to use simple arithmetic operations. For subband coding, the property is important because it reduces hardware complexity.

The construction of an optical subscriber loop and its operation system will be one of the most important infrastructures for the information society of the future. This paper presents a discussion of current and future service trends, the evolution of fiber-optic systems in the loop, and subscriber loop operation systems. Several operation technologies are also discussed which will enable the operation systems described in this paper to be constructed. Of these, the key technologies are an operation system architecture with flexibility, software technologies based on object-oriented design and programming, and automatic operation modules.

In this paper, we consider a class of the languages that have (constant round) perfect zero-knowledge interactive proofs without assuming any complexity assumptions. Especially, we investigate the interactive protocol with the restricted prover who runs in probabilistic polynomial time and knows the complete factorization as a trapdoor information of the integer associated with the input. We give a condition of the existence of constant round perfect zero-knowledge interactive proofs without assuming any complexity assumptions. The bit commitment based on the quadratic residuosity has an important role in our protocol and the simulation is based on the technique developed by Bellare, Micali, and Ostrovsky in Ref. (9), so call double running process. However, the proof of perfect zero-knowledgeness needs a more powerful simulation technique. Our simulation extracts more knowledge, the complete factorization of the integer associated with the input, from a (cheating) verifier than Bellare-Micali-Ostrovsky's simulation does. Furthermore, our main result implies that Blum integer has a five move perfect zero-knowledge interactive proof without assuming any complexity assumptions. (All previous known zero-knowledge protocols for Blum integer required either unproven cryptographic assumptions or unbounded number of rounds of message exchange.)

In this paper we propose a new application of Wu's mechanical theorem proving method to reconstruct polyhedra in 3-D space from their projection image. First we set up three groups of equations. The first group is of the geometric relations expressing that vertices are on a plane segment, on a line segment, and forming angle in 3-D space. The second is of those relations on image plane. And the rest is of the relations between the vertices in 3-D space and their correspondence on image plane. Next, we classify all the groups of equations into two sets, a set of hypotheses and a conjecture. We apply this method to seven cases of models. Then, we apply Wu's method to prove that the hypotheses follow the conjecture and obtain pseudodivided remainders of the conjectures, which represent relations of angles or lengths between 3-D space and their projected image. By this method we obtained new geometrical relations for seven cases of models. We also show that, in the region in image plane where corresponding spatial measures cannot reconstructed, leading coefficients of hypotheses polynomials approach to zero. If the vertex of an image angle is in such regions, we cannot calculate its spatial angle by direct manipulation of the hypothesis polynomials and the conjecture polynomial. But we show that by stability analysis of the pseudodivided remainder the spatial angles can be calculated even in those regions.

A new redundancy technique especially suitable for ultra-high-speed static RAMs (SRAMs) has been developed. This technique is based on a decoding-method that uses two kinds of fuses without introducing any additional delay time. One fuse is initially ON and can be turned OFF afterwards, if necessary, by a cutting process using a focused ion beam (FIB). The other is initially OFF and can be turned ON afterwards by a connecting process using laser chemical vapor deposition (L-CVD). This technique is applied to a 64 kbit SRAM having a 1.5-ns access time. The experimental results obtained through an SRAM chip repaired using this redundancy technique show that this technique does not introduce any increase in the access time and does not reduce the operational margin of the SRAM.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

Global dynamic behavior particularly the bifurcation of periodic orbits of a parallel blower system is studied using a piecewise linear model and the one-dimensional map defined by the Poincare map. First several analytical tools are presented to numerically study the bifurcation process particularly the bifurcation point of the fixed point of the Poincare map. Using two bifurcation diagrams and a bifurcation set, it is shown how periodic orbits bifurcate and leads to chaotic state. It is also shown that the homoclinic bifurcations occur in some parameter regions and that the Li & Yorke conditions of the chaotic state hold in the parameter region which is included in the one where the homoclinic bifurcation occurs. Together with the above, the stable and unstable manifolds of a saddle closed orbit is illustrated and the existence of the homoclinic points is shown.

Low-sensitivity digital filters are required for accurate signal processing. Among many low-sensitivity digital filters, a method using complex allpass circuits is well-known. In this paper, a new synthesis of complex allpass circuits is proposed. The proposed synthesis can be realized more easily either only in the z-domain or in the s-domain than conventional methods. The key concept for the synthesis is based on the factorization of lossless scattering matrices. Complex allpass circuits are interpreted as lossless digital two-port circuits, whose scattering matrices are factored. Furthermore, in the cases of Butterworth, Chebyshev and inverse Chebyshev responses, the explicit formulae for multiplier coefficients are derived, which enable us to synthesize the objective circuits directly from the specifications in the s-domain. Finally design examples verify the effectiveness of the proposed method.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

The main interest of this paper is the theoretical analysis of a recursive periodically time varying digital filter. The generalized transfer function of a recursive periodically time varying digital filter was obtained from its difference equation. It was proved that by making use of the generalized transfer function, we can not only derive the input and output relationship of a recursive periodically time varying digital filter easily but also obtain its equivalent structure effectively. An interesting property of a recursive periodically time varying digital filter was also derived by making use of its generalized transfer function. Moreover, it was completed in this paper the investigation of the generalized transfer functions and impulse responses of other periodically time varying models, including an input sampling polyphase model and an output sampling polyphase model. Meanwhile, the multirate Quadrature Mirror Filter bank system was proved by the authors to be a periodically time varying system. Several examples were also provided to illustrate the effectiveness of using the generalized transfer function to obtain the equivalent structure of a recursive periodically time varying digital filter.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

In this paper, two models for associative memory based on a measure of manhattan length are proposed. First, we propose the two-layered model which has an advantage to its implementation by using PDN. We also refer to the way to improve the recalling ability of this model against noisy input patterns. Secondly, we propose the other model which always recalls the nearest memory pattern in a measure of manhattan length by lateral inhibition. Even if a noise of input pattern is so large that the first model can not recall, this model can recall correctly against such a noisy pattern. We also confirm the performance of the two models by computer simulations.

A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.

We have developed a new functional MOS transistor called Neuron MOSFET (abbreviated as neuMOS or νMOS) which simulates the function of biological neurons. The new transistor is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of weighted summation, all in the voltage mode at a single transistor level. By utilizing its neuron-like very powerful functional capability, various circuits essential for multiple-valued logic operation have been designed using quite simple circuit configurations. The circuit designs for data conversion between the multivalued and binary logic systems and for generating universal literal functions are described and their experimental verifications are presented. One of the most important features of νMOS multivalued lagic circuit is that the circuit operates basically in the voltage mode, thus greatly reducing the power dissipation as compared to the conventional current mode circuitry. This is indeed most essential in implementing multivalued logic systems in ultra large scale integration. Another important feature of νMOS design is in its flexibility of implementing logic functions. The functional form of a universal literal function, for instance, can be arbitrarily altered by external signals without any modifications in its hardware configuration. A circuit representing multiple-valued multithreshold functions is also proposed.

This letter extends the overfitting lattice filter for ARMA parameter estimation with additive noise proposed by Sun and Yahagi. A new way of calculating the lattice parameters is proposed, making their computation truly recursive. This simplifies the method in Ref.(1), and makes it suitable to the parameter estimation of high-order systems.