An efficient reconstruction algorithm for diffraction tomography based on the modified Newton-Kantorovich method is presented and numerically studies. With the Fréchet derivative obtained for the Helmholtz equation, one can derive an iterative formula for getting an object function, which is a function of refractive index of a scatterer. Setting an initial guess of the object function to zero, the pth estimate of the function is obtained by performing the inverse Fourier transform of its spectrum. Since the spectrum is bandlimited within a low-frequency band, the algorithm does not require usual regularization techniques to circumvent ill-posedness of the problem. For numerical calculation of the direct scattering problem, the moment method and the FFT-CG method are utilized. Computer simulations are made for lossless and homogeneous dielectric circular cylinders of various radii and refractive indices. In the iteration process of image reconstruction, the imaginary part of the object function is set to zero with a priori knowledge of the lossless scatterer. Then the convergence behavior of the algorithm remarkably gets improved. From the simulated results, it is seen that the algorithm provides high-quality reconstructed images even for cases where the first-order Born approximation breaks down. Furthermore, the results demonstrate fast convergence properties of the iterative procedure. In particular, we can successfully reconstruct the cylinder of radius 1 wavelength and refractive index that differs by 10% from the surrounding medium. The proposed algorithm is also effective for an object of larger radius.

There have been few studies on formal approaches to the specification and realization of asynchronous sequential circuits. For synchronous sequential circuits, an algebraic method is proposed as one of such approaches, but it cannot be applied to asynchronous ones directly. This paper describes an algebraic method of specifying the abstract behavior of asynchronous sequential circuits. We select an daisy chain arbiter as an example of them. In the arbiter, state transitions are caused by input changes, and all the modules do not always make state transitions simultaneously. These are main obstacles to specify it in the same way as sychronous sequential circuits. In order to remove them, we modify the meaning of input in specifications and introduce pseudo state transitions so that we can regard all the modules as if they make state transitions simultaneously. This method can be applied to most of the other asynchronous sequential circuits.

Rate-based congestion/flow control is a promising way to achieve high throughput in high speed packet-switching networks. We consider a rate-based congestion control to aim at obtaining high throughput and fair sharing of the communication resources. In the scheme, each intermediate node informs its congestion status to the source node. Two kinds of control packets are used for this mechanism. One (a choke packet) is to throttle the rate and another (a loosen packet) is to allow increase of the rate. The source node initiates transmission with a low rate and increases the rate slowly to avoid a rapid increase of the packet queueing at an intermediate node. When the source node receives a choke packet, it decreases the rate rapidly to relieve congestion as soon as possible. The source node upon receipt a loosen packet increases the rate slowly again. We develop a queueing model to investigate the parameter settings to provide a good performance via simulation. The increasing and decreasing parameters of the rate control function are first investigated in various load conditions. We next examine the effect of the queue-length threshold value for the indication of congestion at the intermediate node. The numerical results indicate that the threshold value should be small to obtain a good performance. We finally introduce a technique which accurately recognizes congestion and inhibits an acceptable queueing of the packets at intermediate nodes.

Signature analysis using a Multiple-Input LFSR as the output response compaction circuit is widely adopted in actual BIST schemes. While aliasing probabilities for random errors are usually very small, MI-LFSRs are tend to fail detecting diagonal errors. A spot error, which include the diagonal error as a particular case, is defined as multiple bit crrors adjacent in space and in time domain. Then, shuffling of interconnection between CUT output and MI-LFSR input is studied as a scheme to prevent aliasing for such errors. The condition for preventing aliasing due to a predetermined size of single spot error is shown. Block based shuffling and the shortened one are proposed to realize required distance properties. Effect of shuffling for multiple spot errors is examined by simulation showing that shuffling is effective also for a certain extend of multiple spot errors.

This paper proposes a new adaptive algorithm for acoustic echo cancellers with four times the convergence speed for a speech input, at almost the same computational load, of the normalized LMS (NLMS). This algorithm reflects both the statistics of the variation of a room impulse response and the whitening of the received input signal. This algorithm, called the ESP (exponentially weighted step-size projection) algorithm, uses a different step size for each coefficient of an adaptive transversal filter. These step sizes are time-invariant and weighted proportional to the expected variation of a room impulse response. As a result, the algorithm adjusts coefficients with large errors in large steps, and coefficients with small errors in small steps. The algorithm is based on the fact that the expected variation of a room impulse response becomes progressively smaller along the series by the same exponential ratio as the impulse response energy decay. This algorithm also reflects the whitening of the received input signal, i.e., it removes the correlation between consecutive received input vectors. This process is effective for speech, which has a highly non-white spectrum. A geometric interpretation of the proposed algorithm is derived and the convergence condition is proved. A fast profection algorithm is introduced to reduce the computational complexity and modified for a practical multiple DSP structure so that it requires almost the same computational load, 2L multiply-add operations, as the conventional NLMS. The algorithm is implemented in an acoustic echo canceller constructed with multiple DSP chips, and its fast convergence is demonstrated.

Ac resistivity and power loss values for Mn-Zn ferrite material have been investigated by electrical and magnetic measurements. The ac resistivity shows an inductive dependency on frequency for the low dc resistive samples or for highly dc resistive ones at high temperature, while a capacitive dependency on frequency was observed for the highly resistive materials at the room temperature. These phenomena were interpreted by the dependence of ac resistivity on the dc resistivity, complex permeability and complex permittivity. The dependency of the power losses on the dc resistivity, temperature and frequence were also examined with analysis of power loss term. Dividing the power loss into hysteresis loss and eddy current loss, the frequency dependence of the eddy current loss was found to vary with the magnitude of the dc resistivity as follows: The eddy current loss of low dc resistive materials depends on the dc resistivity. On the other hand, the eddy current loss for high resistive materials is determined by the ac resistivity, contributed from dielectric loss.

An acoustic echo canceller that also cancels room noise is proposed. This system has an additive (noise reference) input port, and a noise canceller (NC) precedes the echo canceller (EC) in a cascade configuration. The adaptation control problem for the cascaded echo and noise canceller is solved by controlling the adaptation process to match the occurrence of intermittent speech/echo; the room noise is a stationary signal. A simulation shows that adaptation using the NLMS algorithm is very effective for the echo and noise cancellation. Sub-band cancelling techniques are utilized. Noise cancellation is realized with a lower band EC. Hardware is implemented and its performance evaluated through experiments under a real acoustic field. The combination of the EC with NC maintains excellent performance at all echo to room noise power ratios. It is shown that the proposed canceller overcomes the disadvantages traditionally associated with ECs and NSc.

A newly developed planar inductor and its application to dc-dc converters are described. The planar inductor consists of a planar spiral coil and soft magnetic sheets, it has a small size (11110.8mm), 33µH inductance and a maximum quality factor of 14. The step down chopper dc-dc converter has been developed by using planar inductor, which has small size (20154mm), 5V-2W typical output and output power/volume ratio of 1.7W/cc. The switching converter can be miniaturized by using the planar inductor.

The characteristics of voltage-resonant dc-dc converters have already been analyzed and described. However, in the conventional analysis, the inductance of the reactor is assumed to be infinity and the loss resistance of the power circuit is not taken into account. Also, in some cases, the averaging method is applied to analyze the resonant dc-dc converters as well as the pwm dc-dc converters. Consequently, the results from conventional analysis are not entirely in agreement with the experimental ones. This paper presents a general design-oriented analysis of the buck-boost type voltage-resonant dc-dc converter in the continuous and discontinuous modes of the reactor current. In this analysis, the loss resistance in each part of the power circuit, the inductance of the reactor, the effective value (not mean value) of the power loss, and the energy-balance among the input, output and internal-loss powers are taken into account. As a result, the behavior and characteristics of the buck-boost type voltage-resonant dc-dc converter are fully explained. It is also revealed that there is a useful mode in the discontinuous reactor current region, in which the output voltage can be regulated sufficiently for the load change from no load to full load and for the relatively large change of the input voltage, and then the change in the switching frequency can be kept relatively small.

A new circuit and a transformer structure is described for a high-input-voltage converter operating at a high switching frequency. The two-MOSFET forward converter is suitable for a high-input-voltage converter. To increase the switching frequency, the reset period of the transformer core flux must be reduced. There are a few methods for decreasing the reset period. Increasing the transformer flyback voltage and reducing its stray capacitance are effective in decreasing the reset period without increasing power loss. A new two-MOSFET forward converter is proposed which uset the increased flyback voltage and a transformer structure to reduce the stray capacitance. The new converter using this transformer provides the basis for a 48-V, 100-W output, 270-V input converter operating at 200kHz with high efficiency (above 95%).

The process of room acoustic planning & design can be aided by Binaural Technology. To this end, a three-stage modelling process is proposed that consists of a "sound"-specification phase, a design phase and a work-plan phase. Binaural recording, reproduction and room simulation techniques are used throughout the three phases allowing for subjective/objective specification and surveillance of the design goals. The binaural room simulation techniques involved include physical scale models and computer models of different complexity. Some basics of binaural computer modelling of room acoustics are described and an implementation example is given. Further the general structure of a software system that tries to model important features of the psychophysics of binaural interaction is reported. The modules of the model are: outer-ear simulation, middle-ear simulation, inner-ear simulation, binaural processors, and the final evaluation stage. Using this model various phenomena of sound localization and spatial hearing, such as lateralization, multiple-image phenomena, summing localization, the precedence effect, and auditory spaciousness, can be simulated. Finally, an interesting application of Binaural Technology is presented, namely, a so called Cocktail-Party-Processor. This processor uses the predescribed binaural model to estimate signal parameters of a desired signal which may be distored by any type of interfering signals. In using this strategy, the system is able to even separate the signals of competitive speakers.

This paper describes a nonstationary spectral analysis method and its application to prognosis and diagnosis of automobiles. An instantaneous frequency spectrum is considered first at a single point of time based on the instantaneous representation of autocorrelation. The spectral distortion is then considered on two-dimensional spectrum, and the filtering is introduced into the instantaneous autocorrelations. By the above procedure, the Instantaneous Covariance method (ICOV), the Instantaneous Maximum Entropy Method (IMEM), and the Wigner method are shown and they are unified. The IMEM is used for the time-dependent spectral estimation of vibration and acoustic sound signals of automobiles. A multi-dimensional (M-D) space is composed based on the variables which are obtained by the IMEM. The M-D space is transformed into a simple two-dimensional (2-D) plane by a projection matrix chosen by the experiments. The proposed method is confirmed useful to analyze nonstationary signals, and it is expected to implement automatic supervising, prognosis and diagnosis for a traffic system.

Under conditions of order reduction, a nonlinear control of a bidirectional coupled-inductor Cuk converter suitable for large-signal applications is presented. The converter is accurately modelled as a second order bilinear system and the conditions established for local stability. The nonlinear control law which is implemented by means of one analog divider, standard operational amplifiers and a pulse-width modulator. As a result, the output variable follows proportionally the reference signal, thus allowing the obtention of different types of power waveforms in the converter output. Experimental results verify the theoretical predictions.

This paper proposes a new fault tolerant intercommunication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed intercommunication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to flow data with one way direction such as a pipeline processing.

To improve the stability and the power supply rejection ratio (PSRR) of the voltage limiter circuit used in high-density DRAM's we present a voltage limiter circuit with pole-zero compensation. Analytical expressions that describe the stability of the circuit are provided for comprehensive consideration of circuit design. Voltage limiters with pole-zero compensation are shown to have excellent performance with respect to the stability, PSRR, and circuit area occupation. The parasitic resistances in internal voltage supply lines, signal transmission lines, and transistors are important parameters determining the stability of pole-zero compensation. Evaluation of a 16-Mbit test device revealed internal voltage fluctuations of 6% during operation of a chip-internal circuit, a phase margin of 53, and a PSRR of 30 dB.

A new design method is proposed for realizing a hypercube network (HC) structured multicomputer system on a wafer using wafer-scale integration (WSI). The probability that an HC can be constructed on a wafer is higher in this method than in the conventional method; this probavility is called a construction probability. We adopt the FUSS method for the processor (PE) address allocation in our desing because it has a high success probability in the allocation. Even if the design renders the address allocation success probalility hegher, it is of no use if it makes either the maximum wiring length between PEs or the array size (wiring area) larger. A new wiring channel structure capable of connecting PEs on a wafer is proposed in this paper, where a channel, called a basic channel, is used. A one-dimensional-array sub-HC row network (RN) or column networks (CN) can be constructed using the basic channel. The sub-HC construction method, which embeds wirings into the basic channel, is also proposed. It requires almost the same wiring width as conventional method. However, it has an advantage in that maximum wiring length between PEs can be about half that of the conventional method. If PEs must be shifted in the case of PE defects, they can be shifted and connected to the basic channel using other PE shifting channels, and an RN or CN can be constructed. The maximum wiring length between PEs, array size, and construction probability will also be derived, and it will be shown that the proposed design is superior to the conventional one.

This paper relates to a novel algorithm for fast estimation of the coefficients of the adaptive FIR filter. The novel algorithm is derived from a first order IIR filter experssion clarifying the estimation process of the NLMS (normalized least mean square) algorithm. The expression shows that the estimation process is equivalent to a procedure extracting the cross-correlation coefficient between the input and the output of an unknown system to be estimated. The interpretation allows to move a subtraction of the echo replica beyond the IIR filter, and the movement gives a construction with the IIR filter coefficient of unity which forms the arithmetic mean. The construction in comparison with the conventional NLMS algorithm, improves the covergence rate extreamly. Moreover, when we use the construction with a simple technique which limits the term of calculating the correlation coefficient in the beginning of a convergence process, the convergence delay becomes negligible. This is a very desirable performance for acoustic echo canceller. In this paper, double-talk and echo path fluctuation are also studied as the first stage for application to acoustic echo canceller. The two subjects can be resolved by introducing two switches and delays into the evaluation process of the correlation coefficient.

In this paper we present and analyze multi-level quorum schemes for maintaining the consistency of replicated data in the presence of concurrency and failures in a large distributed environment. The multi-level quorum method operates on a logical hierarchy of the nodes in the network and applies well known flat voting algorithms for replicated data concurrency control in a layered fashion. We show how the number of hierarchy levels, the number of logical entities per level and the voting algorithms used on each level affect the costs and the degree of availability associated with a wide range of multi-level quorum schemes. The results of the analysis are used to provide guidelines for designing the most suitable multi-level quorum strategy for a given application scenario. Comparative performance measurements in a simulated network are presented to illustrate the properties of multi-level approaches when some of the assumptions of the analytical investigation do not hold.

Strongly Fault-Secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly Code-Disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. This paper presents a new generalized design method for the SFS and SCD realization of combinational circuits. The proposed design is simple, and always gives an SFS and SCD combinational circuit which implements any given logic function. The resulting SFS/SCD circuits can be connected in cascade with each other to construct a larger SFS/SCD circuit if each interface is fully exercised.

This paper describes the derivation of a parallel program from a nondeterministic sequential program using a bottom-up parser as an example. The derivation procedure consists of two stages: exploitation of AND-parallelism and exploitation of OR-parallelism. An interpreter of the sequential parser BUP is first transformed so that processes for the nodes in a parsing tree can run in parallel. Then, the resultant program is transformed so that a nondeterministic search of a parsing tree can be done in parallel. The former stage is performed by hand-simulation, and the latter is accomplished by the compiler of ANDOR-, which is an AND/OR parallel logic programming language. The program finally derived, written in KL1 (Kernel Language of the FGCS Project), achieves an all-solution search without side effects. The program generated corresponds to an interpreter of PAX, a revised parallel version of BUP. This correspondence shows that the derivation method proposed in this paper is effective for creating efficient parallel programs.