The authors proposed an algorithm for calculation of new lower bound (rank bounded distance) using the discrete Fourier transform in 2010. Afterward, we considered some algorithms to improve the original algorithm with moving the row or column. In this paper, we discuss the calculation method of the rank bounded distance by conjugate elements for cyclic codes.

The RO (Ring-Oscillator)-based sensor is one of easily-implementable variation sensors, but for decomposing the observed variability into multiple unique device-parameter variations, a large number of ROs with different structures and sensitivities to device-parameters is required. This paper proposes an area efficient device parameter estimation method with sensitivity-configurable ring oscillator (RO). This sensitivity-configurable RO has a number of configurations and the proposed method exploits this property for reducing sensor area and/or improving estimation accuracy. The proposed method selects multiple sets of sensitivity configurations, obtains multiple estimates and computes the average of them for accuracy improvement exploiting an averaging effect. Experimental results with a 32-nm predictive technology model show that the proposed averaging with multiple estimates can reduce the estimation error by 49% or reduce the sensor area by 75% while keeping the accuracy. Compared to previous work with iterative estimation, 23% accuracy improvement is achieved.

Big data analysis and a data storing applications require a huge volume of storage and a high I/O performance. Applications can achieve high level of performance and cost efficiency by exploiting the high I/O performance of direct attached storages (DAS) such as internal HDDs. With the size of stored data ever increasing, it will be difficult to replace servers since internal HDDs contain huge amounts of data. Generally, the data is copied via Ethernet when transferring the data from the internal HDDs to the new server. However, the amount of data will continue to rapidly increase, and thus, it will be hard to make these types of transfers through the Ethernet since it will take a long time. A storage area network such as iSCSI can be used to avoid this problem because the data can be shared with the servers. However, this decreases the level of performance and increases the costs. Improving the flexibility without incurring I/O performance degradation is required in order to improve the DAS architecture. In response to this issue, we propose FlexDAS, which improves the flexibility of direct attached storage by using a disk area network (DAN) without degradation the I/O performance. A resource manager connects or disconnects the computation nodes to the HDDs via the FlexDAS switch, which supports the SAS or SATA protocols. This function enables for the servers to be replaced in a short period of time. We developed a prototype FlexDAS switch and quantitatively evaluated the architecture. Results show that the FlexDAS switch can disconnect and connect the HDD to the server in just 1.16 seconds. We also confirmed that the FlexDAS improves the performance of the data intensive applications by up to 2.84 times compared with the iSCSI.

Address configuration is a key problem in data center networks. The core issue of automatic address configuration is assigning logical addresses to the physical network according to a blueprint, namely logical-to-device ID mapping, which can be formulated as a graph isomorphic problem and is hard. Recently years, some work has been proposed for this problem, such as DAC and ETAC. DAC adopts a sub-graph isomorphic algorithm. By leveraging the structure characteristic of data center network, DAC can finish the mapping process quickly when there is no malfunction. However, in the presence of any malfunctions, DAC need human effort to correct these malfunctions and thus is time-consuming. ETAC improves on DAC and can finish mapping even in the presence of malfunctions. However, ETAC also suffers from some robustness and efficiency problems. In this paper, we present GA-MAP, a data center networks address mapping algorithm based on genetic algorithm. By intelligently leveraging the structure characteristic of data center networks and the global search characteristic of genetic algorithm, GA-MAP can solve the address mapping problem quickly. Moreover, GA-MAP can even finish address mapping when physical network involved in malfunctions, making it more robust than ETAC. We evaluate GA-MAP via extensive simulation in several of aspects, including computation time, error-tolerance, convergence characteristic and the influence of population size. The simulation results demonstrate that GA-MAP is effective for data center addresses mapping.

In all-optical switches using the cascade of second harmonic generation and difference frequency mixing in periodically poled lithium niobate (PPLN) waveguide devices, walk-off between the fundamental and second harmonic pulses causes crosstalk between neighboring symbols, and limits the switching performance. In this paper, we numerically study retiming characteristics of all-optical switches that employ the PPLN waveguide devices with consideration for the effects of the crosstalk and for the input timing of the data and clock pulses. We find that the time offset between the data and clock pulses can control the timing jitter of the switched output; an appropriate offset can reduce the jitter while improving the switching efficiency.

We propose a method of enhancing the performance of a cross-talk canceller for a four-speaker system with respect to sweet spot size and ringing effect. For the large sweet spot of a cross-talk canceller, the speaker layout needs to be symmetrical to the listener's position. In addition, a ringing effect of the cross-talk canceller is reduced when many speakers are located close to each other. Based on these properties, the proposed method first selects the two speakers in a four-speaker system that are most symmetrical to the target listener's position and then adds the remaining speakers between these two to the final selection. By operating only these selected speakers, the proposed method enlarges the sweet spot size and reduces the ringing effect. We conducted objective and subjective evaluations and verified that the proposed method improves the performance of the cross-talk canceller compared to the conventional method.

Facial age estimation requires accurately capturing the mapping relationship between facial features and corresponding ages, so as to precisely estimate ages for new input facial images. Previous works usually use one-layer regression model to learn this complex mapping relationship, resulting in low estimation accuracy. In this letter, we propose a new gender-specific regression model with a two-layer structure for more accurate age estimation. Different from recent two-layer models that use a global regressor to calculate cumulative attributes (CA) and use CA to estimate age, we use gender-specific ones to calculate CA with more flexibility and precision. Extensive experimental results on FG-NET and Morph 2 datasets demonstrate the superiority of our method over other state-of-the-art age estimation methods.

Soft processors are widely used in FPGA-based embedded computing systems. For such purposes, efficiency in resource utilization is as important as high performance. This paper proposes Ultrasmall, a new soft processor architecture for FPGAs. Ultrasmall supports a subset of the MIPS-I instruction set architecture and employs an area efficient microarchitecture to reduce the use of FPGA resources. While supporting the original 32-bit ISA, Ultrasmall uses a 2-bit serial ALU for all of its operations. This approach significantly reduces the resource utilization instead of increasing the performance overheads. In addition to these device-independent optimizations, we applied several device-dependent optimizations for Xilinx Spartan-3E FPGAs using 4-input lookup tables (LUTs). Optimizations using specific primitives aggressively reduce the number of occupied slices. Our evaluation result shows that Ultrasmall occupies only 84% of the previous small soft processor. In addition to the utilized resource reduction, Ultrasmall achieves 2.9 times higher performance than the previous approach.

Survivability is the capability of a system to provide its services in a timely manner even after intrusion and compromise occur. In this paper, we focus on the quantitative analysis of survivability of virtual machine (VM) based intrusion tolerant system in the presence of Byzantine failures due to malicious attacks. Intrusion tolerant system has the ability of a system to continuously provide correct services even if the system is intruded. This paper introduces a scheme of the intrusion tolerant system with virtualization, and derives the success probability for one request by a Markov chain under the environment where VMs have been intruded due to a security hole by malicious attacks. Finally, in numerical experiments, we evaluate the performance of VM-based intrusion tolerant system from the viewpoint of survivability.

Peer-to-peer (P2P)-Grid systems are being investigated as a platform for converging the Grid and P2P network in the construction of large-scale distributed applications. The highly dynamic nature of P2P-Grid systems greatly affects the execution of the distributed program. Uncertainty caused by arbitrary node failure and departure significantly affects the availability of computing resources and system performance. Checkpoint-and-restart is the most common scheme for fault tolerance because it periodically saves the execution progress onto stable storage. In this paper, we suggest a checkpoint-and-restart mechanism as a fault-tolerant method for applications on P2P-Grid systems. Failure detection mechanism is a necessary prerequisite to fault tolerance and fault recovery in general. Given the highly dynamic nature of nodes within P2P-Grid systems, any failure should be detected to ensure effective task execution. Therefore, failure detection mechanism as an integral part of P2P-Grid systems was studied. We discussed how the design of various failure detection algorithms affects their performance in average failure detection time of nodes. Numerical analysis results and implementation evaluation are also provided to show different average failure detection times in real systems for various failure detection algorithms. The comparison shows the shortest average failure detection time by 8.8s on basis of the WP failure detector. Our lowest mean time to recovery (MTTR) is also proven to have a distinct advantage with a time consumption reduction of about 5.5s over its counterparts.

The role of an optical low-pass filter (OLPF) in a digital still camera is to remove the high spatial frequencies that cause aliasing, thereby enhancing the image quality. However, this also causes some loss of detail. Yet, when an image is captured without the OLPF, moiré generally appears in the high spatial frequency region of the image. Accordingly, this paper presents a moiré reduction method that allows omission of the OLPF. Since most digital still cameras use a CCD or a CMOS with a Bayer pattern, moiré patterns and color artifacts are simultaneously induced by aliasing at high spatial frequencies. Therefore, in this study, moiré reduction is performed in both the luminance channel to remove the moiré patterns and the color channel to reduce color smearing. To detect the moiré patterns, the spatial frequency response (SFR) of the camera is first analyzed. The moiré regions are identified using patterns related to the SFR of the camera and then analyzed in the frequency domain. The moiré patterns are reduced by removing their frequency components, represented by the inflection point between the high-frequency and DC components in the moiré region. To reduce the color smearing, color changing regions are detected using the color variation ratios for the RGB channels and then corrected by multiplying with the average surrounding colors. Experiments confirm that the proposed method is able to reduce the moiré in both the luminance and color channels, while also preserving the detail.

The present paper introduces a novel method for the construction of a class of sequences that have a zero-correlation zone. For the proposed sequence set, both the cross-correlation function and the side lobe of the auto-correlation function are zero for phase shifts within the zero-correlation zone. The proposed scheme can generate a set of sequences of length 8n2 from an arbitrary Hadamard matrix of order n and a set of 2n trigonometric-like function sequences of length 4n. The proposed sequence construction can generate an optimal zero-correlation zone sequence set that satisfies the theoretical bound on the number of members for the given zero-correlation zone and sequence period. The auto-correlation function of the proposed sequence is equal to zero for all nonzero phase shifts. The peak factor of the proposed sequence set is √2, and the peak factor of a single trigonometric function is equal to √2. Assigning the sequences of the proposed set to a synthetic aperture ultrasonic imaging system would improve the S/N of the obtained image. The proposed sequence set can also improve the performance of radar systems. The performance of the applications of the proposed sequence sets are evaluated.

As the use of information technology is rapidly expanding, the power consumption of IT equipment is becoming an important social issue. As such, the power supply of IT equipment must provide various power saving measures through advanced features. A digitally controlled power supply is attractive for satisfying this requirement due to its flexibility and advanced management functionality. However, a digitally controlled power supply has issues with its transient response performance because the conversion time of the analog-digital converter and the time required for digital processing in the digital controller adversely affect the dynamic characteristics. The present paper introduces a new approach that can improve the transient response performance of the digital point-of-load (POL) power supplies of computer processors. The resulting power systems use feed-forward transient control, in addition to the general voltage regulation feedback control loop, to improve their dynamic characteristics. On the feed-forward control path, the processor workload information is supplied to the power supply controller from the processor. The power supply controller uses the workload information to predict the power load change and generates an auxiliary control to improve the transient response performance. As the processor workload information, the processor-integrated performance counter values are sent to the power supply controller via a hardware interface. The processor power consumption prediction equation is modeled using the moving average model, which uses performance counter values of several past steps. The prediction equation parameters are defined by multiple regression analysis using the measured CPU power consumption data and experimentally obtained performance counter information. The analysis reveals that the optimum parameters change with time during transient periods. The modeled equation well explains the processor power load change. The measured CPU power consumption profile is confirmed to be accurately replicated by the prediction for a period of 200ns. Using the power load change prediction model, circuit simulations of the feed-forward transient control are conducted. It is validated that the proposed approach improves power supply transient response under some practical server workloads.

A novel approach for the multiple-model multi-sensor Bernoulli filter (MM-MSBF) based on the theory of finite set statistics (FISST) is proposed for a single maneuvering target tracking in the presence of detection uncertainty and clutter. First, the FISST is used to derive the multi-sensor likelihood function of MSBF, and then combining the MSBF filter with the interacting multiple models (IMM) algorithm to track the maneuvering target. Moreover, the sequential Monte Carlo (SMC) method is used to implement the MM-MSBF algorithm. Eventually, the simulation results are provided to demonstrate the effectiveness of the proposed filter.

Content centric networking (CCN) is a newly proposed futuristic Internet paradigm in which communication depends on the decoupling of content names from their locations. In CCN-based multihop wireless ad hoc networks, the participating nodes show dynamic topology, intermittent connectivity, channels fluctuation, and severe constraints such as limited battery power. In the case of traffic congestion, the affected nodes die early owing to the shortage of battery power. Consequently, all pending request entries are also destroyed, which further degrades the network performance as well as the node working lifetime. In this study, we have proposed a novel energy aware transmission scheme in which the forwarding mechanism is based on a node's residual energy. The proposed scheme is evaluated using official ndnSIM. This scheme enhances performance in terms of content retrieval time and total Interest transmission in the network.

Determining an effective way to reduce computation complexity is an essential task for adaptive echo cancellation applications. Recently, a family of partial update (PU) adaptive algorithms has been proposed to effectively reduce computational complexity. However, because a PU algorithm updates only a portion of the weights of the adaptive filters, the rate of convergence is reduced. To address this issue, this paper proposes an enhanced switching-based variable step-size (ES-VSS) approach to the M-max PU least mean square (LMS) algorithm. The step-size is determined by the correlation between the error signals and their noise-free versions. Noise-free error signals are approximated according to the level of convergence achieved during the adaptation process. The approximation of the noise-free error signals switches among four modes, such that the resulting step-size is as close to its optimal value as possible. Simulation results show that when only a half of all taps are updated in a single iteration, the proposed method significantly enhances the convergence rate of the M-max PU LMS algorithm.

The primitive called public key encryption with non-interactive opening (PKENO) is a class of public key encryption (PKE) with additional functionality. By using this, a receiver of a ciphertext can prove that the ciphertext is an encryption of a specified message in a publicly verifiable manner. In some situation that a receiver needs to claim that a ciphertext is NOT decrypted to a specified message, if he/she proves the fact by using PKENO straightforwardly, the real message of the ciphertext is revealed and a verifier checks that it is different from the specified message about which the receiver wants to prove. However, this naive solution is problematic in terms of privacy. Inspired by this problem, we propose the notion of disavowable public key encryption with non-interactive opening (disavowable PKENO) where, with respect to a ciphertext and a message, the receiver of the ciphertext can issue a proof that the plaintext of the ciphertext is NOT the message. Also, we give a concrete construction. Specifically, a disavowal proof in our scheme consists of 61 group elements. The proposed disavowable PKENO scheme is provably secure in the standard model under the decisional linear assumption and strong unforgeability of the underlying one-time signature scheme.

This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27×0.36mm2, is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25°C is 3µs. The average reduction energy is at least 42% from 0°C to 100°C.

ThruChip interface (TCI) is an emerging wireless interface in three-dimensional (3-D) integrated circuit (IC) technology. However, the TCI physical design guidelines remain unclear. In this paper, a ThruChip test chip is designed and fabricated for design guidelines exploration. Three inductive coupling interface physical design scenarios, baseline, power mesh, and dummy metal fill, are deployed in the test chip. In the baseline scenario, the test chip measurement results show that thinning chip or enlarging coil dimension can further reduce TCI power. The power mesh scenario shows that the eddy current on power mesh can dramatically reduce magnetic pulse signal and thus possibly cause TCI to fail. A power mesh splitting method is proposed to effectively suppress eddy current impact while minimizing power mesh structure impact. The simulation results show that the proposed method can recover 77% coupling coefficient loss while only introducing additional 0.5% IR-drop. In dummy metal fill case, dummy metal fill enclosed within TCI coils have no impact on TCI transmission and thus are ignorable.

Face verification in the presence of age progression is an important problem that has not been widely addressed. Despite appearance changes for same person due to aging, they are more similar compared to facial images from different individuals. Hence, we design common and adapted vocabularies, where common vocabulary describes contents of general population and adapted vocabulary represents specific characteristics of one of image facial pairs. And the other image is characterized with a concatenation histogram of common and adapted visual words counts, termed as “age-invariant distinctive representation”. The representation describes whether the image content is best modeled by the common vocabulary or the corresponding adapted vocabulary, which is further used to accomplish the face verification. The proposed approach is tested on the FGnet dataset and a collection of real-world facial images from identification card. The experimental results demonstrate the effectiveness of the proposed method for verification of identity at a modest computational cost.