An earthquake is a destructive natural disaster, which cannot be predicted accurately and causes devastating damage and losses. In fact, many of the damages can be prevented if people know what to do during and after earthquakes. Earthquake education is the most important method to raise public awareness and mitigate the damage caused by earthquakes. Generally, earthquake education consists of conducting traditional earthquake drills in schools or communities and experiencing an earthquake through the use of an earthquake simulator. However, these approaches are unrealistic or expensive to apply, especially in underdeveloped areas where earthquakes occur frequently. In this paper, an earthquake drill simulation system based on virtual reality (VR) technology is proposed. A User is immersed in a 3D virtual earthquake environment through a head mounted display and is able to control the avatar in a virtual scene via Kinect to respond to the simulated earthquake environment generated by SIGVerse, a simulation platform. It is a cost effective solution and is easy to deploy. The design and implementation of this VR system is proposed and a dormitory earthquake simulation is conducted. Results show that powerful earthquakes can be simulated successfully and the VR technology can be applied in the earthquake drills.

The tree-based routing approach has been known as an efficient method for node mobility management and data packet transmission between two long-distance parties; however, its parameter adjustment must balance control overhead against the convergence speed of topology information according to node mobility. Meanwhile, location-based routing works more efficiently when the distance between the source and destination is relatively short. Therefore, this paper proposes a roadside unit (RSU) based hybrid routing protocol, called RSU-HRP that combines the strengths of both protocols while offsetting their weaknesses. In RSU-HRP, the tree construction is modified to take into account the link and route quality to construct a robust and reliable tree against high node mobility, and an optimized broadcast algorithm is developed to reduce control overhead induced by the advertisement message periodically sent from a roadside unit. In addition, the two routing methods are selectively used based on the computed distance in hops between a source and a destination. Simulation results show that RSU-HRP far outperforms TrafRoute in terms of packet delivery ratio, end-to-end delay, and control overhead in both Vehicle-to-Infrastructure and Vehicle-to-Vehicle communication models.

We conduct, in accordance with IEC 61000-4-2, an electrostatic discharge (ESD) test for a small size battery-operated control circuit board in a myoelectric artificial hand system to investigate the influence of the induced noises by indirect ESDs from an ESD generator to a horizontal coupling plane (HCP) and a vertical coupling plane (VCP). A photo-coupler is set between the small size control board and a motor control circuit to suppress noise in the pulse width modulation (PWM) signals. Two types of ESD noise are observed at the output pins of PWM signals. One type is the ESD noise itself (called Type A) and the other one is the ESD noise superimposed over the PWM pulses (Type B). No matter which polarity the charge voltages of the ESD generator have, both types can be observed and the Type A is dominant in the output pulses. Moreover, the ESD interference in the HCP case is found to be stronger than that in the VCP case usually. In the PWM signals observed at the photo-coupler output, on the other hand, Type A noises tend to increase for positive polarity and decrease for negative polarity, while Type B noises tend to increase at -8kV test level in the HCP case. These results suggest that the photo-coupler does not work well for ESD noise suppression. One of the reasons has been demonstrated to be due to the driving capability of the photo-coupler, and other one is due to the presence of a parasitic capacitance between the input and output of the photo-coupler. The parasitic capacitance can yield a capacitive coupling so that high-frequency ESD noises pass through the photo-coupler.

The two-dimensional (2D) interference is one of the major impairments in bit-patterned media recording (BPMR) systems due to small bit and track pitches, especially at high recording densities. To alleviate this problem, we introduced a rate-4/5 constructive inter-track interference (CITI) coding scheme to prevent the destructive data patterns to be written onto a magnetic medium for an uncoded BPMR system, i.e., without error-correction codes. Because the CITI code produces only the hard decision, it cannot be employed in a coded BPMR system that uses a low-density parity-check (LDPC) code. To utilize it in an iterative decoding scheme, we propose a soft CITI coding scheme based on the log-likelihood ratio algebra implementation in Boolean logic mappings in order that the soft CITI coding scheme together with a modified 2D soft-output Viterbi algorithm (SOVA) detector and a LDPC decoder will jointly perform iterative decoding. Simulation results show that the proposed scheme provides a significant performance improvement, in particular when an areal density (AD) is high and/or the position jitter is large. Specifically, at a bit-error rate of 10-4 and no position jitter, the proposed system can provide approximately 1.8 and 3.5 dB gain over the conventional coded system without using the CITI code at the ADs of 2.5 and 3.0 Tera-bit per square inch (Tb/in2), respectively.

In this paper, we propose SimCS (similarity based on contribution scores) to compute the similarity of scientific papers. For similarity computation, we exploit a notion of a contribution score that indicates how much a paper contributes to another paper citing it. Also, we consider the author dominance of papers in computing contribution scores. We perform extensive experiments with a real-world dataset to show the superiority of SimCS. In comparison with SimCC, the-state-of-the-art method, SimCS not only requires no extra parameter tuning but also shows higher accuracy in similarity computation.

We propose the concept of an integrated coherent photonic wireless transmitter based on the simultaneous injection locking of two monolithically integrated distributed feedback (DFB) laser diodes (LDs) using an optical frequency comb (OFC). We characterize the basic operation of the transmitter and demonstrate that two injection-locked integrated DFB LDs are sufficiently stable to generate the carrier signal using a uni-traveling-carrier photodiode (UTC-PD) for a real-time error-free (bit error rate: BER < 10-11) coherent transmission with a data rate of 10 Gbit/s at a carrier frequency of 97 GHz. In the coherent wireless transmission, we compare the BER characteristics of the injection-locked transmitter with that of an actively phase-stabilized transmitter and show that the power penalty of 8-dB for the injection-locked transmitter is due to the RF spurious components, which can be reduced by integrating the OFC generator (OFCG) and LDs on the same chip. Our results suggest that the integration of the OFCG, DFB LDs, modulators, semiconductor optical amplifiers, and UTC-PD on the same chip is a promising strategy to develop a practical real-time ultrafast coherent millimeter/terahertz wave wireless transmitter.

In this paper, we propose Configurable Query Processing Hardware (CQPH), an FPGA-based accelerator for continuous query processing over data streams. CQPH is a highly optimized and minimal-overhead execution engine designed to deliver real-time response for high-volume data streams. Unlike most of the other FPGA-based approaches, CQPH provides on-the-fly configurability for multiple queries with its own dynamic configuration mechanism. With a dedicated query compiler, SQL-like queries can be easily configured into CQPH at run time. CQPH supports continuous queries including selection, group-by operation and sliding-window aggregation with a large number of overlapping sliding windows. As a proof of concept, a prototype of CQPH is implemented on an FPGA platform for a case study. Evaluation results indicate that a given query can be configured within just a few microseconds, and the prototype implementation of CQPH can process over 150 million tuples per second with a latency of less than a microsecond. Results also indicate that CQPH provides linear scalability to increase its flexibility (i.e., on-the-fly configurability) without sacrificing performance (i.e., maximum allowable clock speed).

We present a low-voltage digitally-controlled oscillator (DCO) with the third-order ΔΣ modulator utilized in the medical implant communication service (MICS) frequency band. An optimized DCO core operating in the subthreshold region is designed, based on the gm/ID methodology. Thermometer coder with the dynamic element matching and ΔΣ modulator are implemented for the frequency tuning. High frequency resolution is achieved by using the ΔΣ modulator. The ΔΣ-modulator-based LC-DCO implemented in a 130-nm CMOS technology has achieved the phase noise of -115.3 dBc/Hz at 200 kHz offset frequency with the tuning range of 382 MHz to 412 MHz for the MICS band. It consumes 700 µW from a 0.7-V supply voltage and has a high frequency resolution of 18 kHz.

In this paper, the repeatable hybrid parallel implementation of inverse matrix computation using SMW formula is proposed. The authors' had previously proposed a hybrid parallel algorithm for inverse matrix computation. It is reasonably fast for a one time computation of an inverse matrix, but it is hard to apply this algorithm repeatedly for consecutive computations since the relocation of the large matrix is required at the beginning of each iterations. In order to eliminate the relocation of the large input matrix which is the output of the inverse matrix computation from the previous time step, the computation algorithm has been redesigned so that the required portion of the input matrix becomes the same as the output portion of the previously computed matrix in each node. This makes it possible to repeatedly and efficiently apply the SMW formula to compute inverse matrix in a time-series simulation.

This paper describes the circuit design and measurement results of a new GaAs-HBT RF power detector proposed for use in WiMAX and wireless LAN transmitter applications. The detector, which is based on a simple current-mirror topology, occupies a small die area. It is, therefore, not only easy to implement together with a GaAs-HBT power amplifier, but can also offer approximately logarithmic (linear-in-dB) characteristics. Because it can also be driven with small voltage amplitudes, it is suitable for base-terminal monitoring at an HBT power stage. When the detector is used as a base-terminal power monitor, an appropriate base resistance added to the detection HBT effectively suppresses frequency dispersion of the detected voltage characteristics. Measurements of a prototype detector incorporated into a single-stage HBT power amplifier fabricated on the same die are as follows. The detector is capable of delivering a detected voltage of 0.35-2.5 V with a slope of less than 0.17 V/dB over a 4-to-24-dBm output power range at 3.5 GHz while drawing a current of less than 1.8 mA from a 2.85-V supply. While satisfying a log conformance error of less than 1 dB over an amplifier output power range from 4 dBm to 24 dBm, it can also suppress the detected power dispersion within 0.18 dB at approximately 15 dBm of output power over a 3.1-3.9-GHz-wide frequency range. This dispersion value is approximately one-tenth that of a conventional collector-terminal-monitor-type diode detector.

A novel dynamic element matching (DEM) method, called binary-tree random DEM (BTR-DEM), is presented for a Nyquist-rate current-steering digital-to-analog converter (DAC). By increasing or decreasing the number of unit current sources randomly at the same time, the BTR-DEM encoding reduces switch transition glitches. A 5-bit current-steering DAC with the BTR-DEM technique is implemented in a 65-nm CMOS technology. The measured spurious free dynamic range (SFDR) attains 42 dB for a sample rate of 100 MHz and shows little dependence on signal frequency.

Outsourcing IC design and fabrication is one of the effective solutions to reduce design cost but it may cause severe security risks. Particularly, malicious outside vendors may implement Hardware Trojans (HTs) on ICs. When we focus on IC design phase, we cannot assume an HT-free netlist or a Golden netlist and it is too difficult to identify whether a given netlist is HT-free or not. In this paper, we propose a score-based hardware-trojans identifying method at gate-level netlists without using a Golden netlist. Our proposed method does not directly detect HTs themselves in a gate-level netlist but it detects a net included in HTs, which is called Trojan net, instead. Firstly, we observe Trojan nets from several HT-inserted benchmarks and extract several their features. Secondly, we give scores to extracted Trojan net features and sum up them for each net in benchmarks. Then we can find out a score threshold to classify HT-free and HT-inserted netlists. Based on these scores, we can successfully classify HT-free and HT-inserted netlists in all the Trust-HUB gate-level benchmarks and ISCAS85 benchmarks as well as HT-free and HT-inserted AES gate-level netlists. Experimental results demonstrate that our method successfully identify all the HT-inserted gate-level benchmarks to be “HT-inserted” and all the HT-free gate-level benchmarks to be “HT-free” in approximately three hours for each benchmark.

In the routing design of interposer and etc., the combination of a pin pair to be connected by wire is often flexible, and the reductions of the total wire length and the length difference are pursued to keep the circuit performance. Even though the total wire length can be minimized by finding a minimum cost maximum flow in set pair routing problems, the length difference is often large, and the reduction of it is not easy. In this paper, an algorithm that reduces the length difference while keeping the total wire length small is proposed. In the proposed algorithm, an initial routing first obtained by a minimum cost maximum flow. Then it is modified to reduce the maximum length while keeping the minimum total wire length, and a connection of the minimum length is detoured to reduce the length difference. The effectiveness of the proposed algorithm is confirmed by experiments.

In this paper, we propose a method for designing finite impulse response (FIR) filters with canonic signed digit (CSD) coefficients using particle swarm optimization (PSO). In such a design problem, a large number of local minimums appear in an evaluation function for the optimization. An updating procedure of PSO tends to stagnate around such local minimums and thus indicates a premature convergence property. Therefore, a new framework for avoiding such a situation is proposed, in which the evaluation function is modified around the stagnation point. Several design examples are shown to present the effectiveness of the proposed method.

Reduced-reference (RR) image quality assessment (IQA) algorithm aims to automatically evaluate the distorted image quality with partial reference data. The goal of RR IQA metric is to achieve higher quality prediction accuracy using less reference information. In this paper, we introduce a new RR IQA metric by quantifying the difference of discrete cosine transform (DCT) entropy features between the reference and distorted images. Neurophysiological evidences indicate that the human visual system presents different sensitivities to different frequency bands. Moreover, distortions on different bands result in individual quality degradations. Therefore, we suggest to calculate the information degradation on each band separately for quality assessment. The information degradations are firstly measured by the entropy difference of reorganized DCT coefficients. Then, the entropy differences on all bands are pooled to obtain the quality score. Experimental results on LIVE, CSIQ, TID2008, Toyama and IVC databases show that the proposed method performs highly consistent with human perception with limited reference data (8 values).

For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAs with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.

Route guidance system is one of the essential components of a vehicle navigation system in ITS. In this paper, a centrally determined route guidance system is established to solve congestion problems. The Sarsa learning method is used to guide vehicles, and global and local parameter strategy is proposed to adjust the vehicle guidance by considering the whole traffic system and local traffic environment, respectively. The proposed method can save the average driving time and relieve traffic congestion. The evaluation was done using two cases on different road networks. The experimental results show the efficiency and effectiveness of the proposed algorithm.

This paper introduces a fast image denoising algorithm by estimating noise parameters without prior information about the noise. Under the assumption that additive noise has a Gaussian distribution, the noise parameters were estimated from an observed degraded image, and were used to define the constraints of a noise detection process that was coupled with a Markov random field (MRF). In addition, an adaptive modified weighted Gaussian filter with variable window sizes defined by the constraints on noise detection was used to control the degree of smoothness of the reconstructed image. Experimental results demonstrate the capability of the proposed algorithm.

In this paper, we consider the Reed-Solomon codes over Fqm with evaluations in a subfield Fq. By the “virtual extension”, we can embed these codes into homogeneous interleaved Reed-Solomon codes. Based on this property and the collaborative decoding algorithm, a new probabilistic decoding algorithm that can correct errors up to $rac{m}{m+1}(n-k)$ for these codes is proposed. We show that whether the new decoding algorithm fails or not is only dependent on the error. We also give an upper bound on the failure probability of the new decoding algorithm for the case s=2. The new decoding algorithm has some advantages over some known decoding algorithms.

The conventional non-negative matrix factorization (NMF)-based speech enhancement is accomplished by updating iteratively with the prior knowledge of the clean speech and noise spectra bases. With the probabilistic estimation of whether the speech is present or not in a certain frame, this letter proposes a speech enhancement algorithm incorporating the speech presence probability (SPP) obtained via noise estimation to the NMF process. To take advantage of both the NMF-based and statistical model-based approaches, the final enhanced speech is achieved by applying a statistical model-based filter to the output of the SPP weighted NMF. Objective evaluations using perceptual evaluation of speech quality (PESQ) on TIMIT with 20 noise types at various signal-to-noise ratio (SNR) levels demonstrate the superiority of the proposed algorithm over the conventional NMF and statistical model-based baselines.