This paper describes an analytic method, experimental results and simulation results for self-heating in a SOI (Silicon On Insulator) high voltage MOS transistor. The new analytic method enabled the temperature-rise caused by self-heating to be measured precisely. The temperature-rise in an operating transistor was evaluated by measuring the change of the source current against the source current without the self-heating. In advance, the relation between the temperature-rise and the current change had been prepared by measuring the current decrease when the hot-chuck temperature had been changed in iso-thermal condition. By using this method, the dependence of the temperature-rise or the current decrease on the operating condition or the thermal resistance were clarified. Furthermore, these measurement results and the thermal resistance which is calculated by a FEM analysis enabled a fully coupled electrothermal device simulation to be analyzed more precisely. The dependence of the current decrease on the buried oxide thickness were also calculated.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

The progress of multimedia applications for education, research, social welfare and commerce is generating a lot of interest in the potential of a combination of satellite networking and Internet technology. The combination is particularly attractive as a low cost solution in regions which are large and sparsely populated. In 1991, aiming at networking the Pan-Pacific region, the PARTNERS (Pan-Pacific Regional Telecommunications Network Experiment and Research by Satellite) project was initiated. In this project, the major target was to construct a satellite-based network infrastructure to support education, research and so on in the Pan-Pacific region. As a part of PARTNERS the MEISEI-NET (Multimedia EducatIon System using satellite ETS-V and InterNET) project was started to evaluate the utility of satellite networking for education and reserch and, to investigate the feasibility of expanding the reach of the Internet using the PARTNERS infrastructure. MEISEI-NET focussed on (1) low start-up cost, (2) open access to the rich information resources on the Internet, (3) use of network to support education and research, and , (4) development and distribution of software for MEISEI-NET users. The construction of MEISEI-NET will be detailed followed by a report on its usage and the effects of this network. To support and manage MESEI-NET operations, we developed and deployed SNMP-based intelligent network management system. It offered fault detection and notification. This made the MEISEI-NET robust and practical despite of the satellite's (ETS-V) drift-problem. Students and researchers of universities from different countries participated in and benefited from MEISEI-NET until March 1996.

A method called "active guard band filtering" is proposed for reducing substrate noise in analog and digital mixed-signal integrated circuits. A noise cancellation signal having an inverse value to the substrate noise is actively input into a guard band to suppress the substrate noise. An operational amplifier produces the noise cancellation signal based upon the substrate noise detected by one guard band and feeds this signal through another quard band into the substrate. This is done within the amplifier feedback loop, which includes the guard bands and the substrate. The noise suppression effect was measured by using 0.8µm CMOS test chip. Using active guard band filtering suppressed substrate noise to -40 dB of the original non-canceled noise level at 8 MHz. The noise suppression effect was also observed at frequencies up to 20MHz, with an external operational amplifier. The influence of parasitic impedance was found to be a key factor in noise suppression. An active guard band filter with an on-chip noise cancellation circuit will be even more effective for high frequencies, because it eliminates parasitic impedance due to external components.

This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission such as Fiber-To-The-Home (FTTH). It enables to the handling of asynchronous burst-mode data. Without an external reference clock signal, it can make a quick extraction of clock signal from received data packets using a "gating-timing circuit" and a "burst PLL." The gating-timing circuit employs bit gating for a quick phase response, and the burst PLL employs frame gating for quick frequency adjustment to differences between packets and clock extraction. This circuit has a simple configuration without any external oscillators, which reduces both cost and power. A fabricated 0.5-µm CMOS IC exhibits instantaneous response within one bit for 156 Mb/s asynchronous data packets.

Photovoltaic devices capable of generating more than 200 volts with an area of 1 cm2 have been developed for directly driving microactuators such as piezoelectric or electrostatic actuators. The micro-devices interconnect 285 micro cells (unit cell size: about 0.5 mm 2.0 mm) in series, and have an open circuit voltage (Voc) of 207 volts, a short circuit current (Isc) of 36.6 µA, a maximum output power (Pmax) of 4.65 mW and a fill factor (F.F.) of 0.615 under AM (Air Mass) 1.5 and 100 mW/cm2 illumination. This voltage is the highest in the world for the area of 1 cm2. The series connection is precisely processed by a focused laser beam, thereby significantly reducing the area needed for device connections. It has been confirmed that a piezoelectric polymer can be directly driven by the electrical output in evaluating the potential of the devices to be used as a microactuator's power source.

This paper discusses the problems in designing virtual-path (VP) networks and underlying transmission-path (TP) networks using the "self-sizing" capability. Self-sizing implies an autonomous adjustment mechanism for VP bandwidths based on traffic conditions observed in real time. The notion of "bandwidth demand" has been introduced to overcome some of the problems with VP bandwidth sizing, e.g., complex traffic statistics and diverse quality of service requirements. Using the bandwidth demand concept, a VP-bandwidth-sizing procedure is proposed in which real-time estimates of VP bandwidth demand and successive VP bandwidth allocation are jointly utilized. Next, TP bandwidth demand, including extra capacity to cover single-link failures, is defined and used to measure the congestion level of the TP. Finally, a TP provisioning method is proposed that uses TP "lifetime" analysis.

In this paper, an efficient one-way point-to-multipoint communication protocol (PTMP) is proposed. The PTM protocol is helpful to distribute information to many workstations simultaneously and correctly. The PTM protocol is designed for network channels with low error possibility. The PTM protocol utilizes broadcast for data distributing. Re-transmission request for lost packet is returned to the server, and acknowledgment for correctly received packets is not returned to the server. We have applied the protocol to the network presentation system. The network presentation system is intended to display same graphical images to multiple workstations simultaneously on an X window system. This presentation system is able to provide services for at least forty X servers simultaneously, the capacity is limited to X server performance, except for pixmap drawing. For the case of pixmap drawing, the system capacity is limited to the network bandwidth. To solve network bandwidth problem, we combined PTM protocol with the network presentation system. With PTM protocol, system performance is improved and the use of network bandwidth is lowered.

In the information engineering learning environment, there may be more than one solution to any given problem. We have developed CAMELOT using the Nominal Group Technique for group problem solving. This paper describes the collaborative learning system on the Internet using discussion model, the effectiveness of collaborative learning in modeling the entity-relationship diagram within the field of information engineering, and how to apply AI technologies such as rule-based reasoning and case-based reasoning to the pedagogical strategy. By using CAMELOT, each learner learns how to analyze through case studies and how to collaborate with his or her group in problem solving. As a result. We have found evidence for the effectiveness of collaborative learning, such as getting a deeper understanding by using CAMELOT than by individual learning, because they can reach better solutions through discussion, tips from other learners, examination of one another's individual solutions, and understanding alternative solutions using case-based reasoning.

The present paper describes a novel approach to interconnecting and assembling components of MEMS at room temperature. The main drawback of the conventional bonding methods is their rather high process temperatures. The new method, which is referred as the surface activated bonding (SAB), utilizes the phenomena of the adhesion between two atomically clean solid surfaces to enable the bonding at lower temperature or even at room temperature. In the bonding procedure, the surfaces to be bonded are merely brought into contact after sputter-cleaning by Ar fast atom in ultrahigh vacuum conditions. TEM observations of the bonded interfaces show that a direct bonding in atomic scale is achieved in the interface between the micro-components. Based on the concept of this new bonding technology, a micro-assembly system was developed. The micro-assembly system is operated by means of a virtual manipulation system in which 3D model of the micro-components are manipulated virtually in a computer graphics constructed in the world wide web (WWW) scheme. The micro-assembly system will provide a new design tool of three dimensional MEMS by combining the possibility of the flexible assembly and the intuitive operations.

This letter presents a realization of active current-mode resonator with complex coefficients using CCIIs. The resonator can be used for cascade or leapfrog configuration of high-order bandpass filters with complex coefficients. For realizing the resonators, only the grounded capacitors and the grounded resistors as passive elements are required, therfore the resonator is suitable for the integrated circuit realization. The letter shows that the response error of the proposed circuit caused by nonideality of active components is more easily compensated than that of voltage-mode counterpart. Experimental result is used for verifying the feasibility of the proposed resonator.

Digital-switching noise coupled into sensitive analog circuits is a critical problem in large-scale integration of mixed analog and digital circuits. This paper describes noise coupling of this kind, especially, through the substrate in CMOS integrated circuits, and reviews recent technical solutions to this noise problem. Simplified models have been developed to simulate the substrate coupling rapidly and accurately. A method using a CMOS comparator was proposed for measuring the effects of substrate noise, and equivalent waveforms of actual substrate noise were obtained. A circuit tecnique, called active guard band filtering, that controls the noise source is a new approach to substrate noise decoupling. CAD methods for handling substrate-coupled switching noise are making design verification possible for practical mixed-signal LSIs.

In this paper, two types of improved CMRR CMOS OAs, N type and P type, without common-mode feedback and the cascode current mirrors, are proposed. The CMRR of proposed OAs are enhanced by compensating variations in tail bias current, caused by a common mode input signal, at the differential input stage, by means of feedforward controlled current source. Simulation results show that the CMRR of the proposed OAs are 20dB higher than that of conventional OAs.

Integrating the power supply and signal processing circuit into one chip is an important step towards achieving a system-on-chip. This paper reviews and looks at the current technologies and their trends for power supply components such as DC-DC converters, intelligent power LSIs, and thin-film magnetic devices for the system-on-chip. A device structure has been proposed for the system-on-chip that is based on a quasi-SOI technique, in which the buried oxide layer is partially removed from the SOI substrate. In this structure, the CMOS devices for the digital signal-processing circuit and the bipolar transistors are formed in a conventional SOI region, and the CMOS analog devices and high-voltage devices are formed in a quasi-SOI region.

A new structure for adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error is introduced and the mathematical background for the soulution of the related adaptive filtering problem is derived. The presented structure gives rise to AR spectral estimates that represent the true underlying spectrum with better fidelity than conventional LS methods by allowing an arbitrary trade-off between variance of spectral estimates and tracking ability of the estimator along the frequency spectrum. The linear prediction error is decomposed through a filter bank and components of each band are analyzed by different window lengths, allowing long windows to track slowly varying signals and short windows to observe fastly varying components. The correlation matrix of the input signal is shown to satisfy both time-update and order-update properties for rectangular windowing functions, and an RLS algorithm based on each property is presented. Adaptive forward and backward relations are used to derive a mathematical framework that serves as a basis for the design of fast RLS alogorithms. Also, computer experiments comparing the performance of conventional and the proposed multi-band methods are depicted and discussed.

We propose an nn optical switch that is suitable for flexible and reliable optical access networks and for reconfigurable optical inter-module connections in large-scale processing systems. The switch consists of an intersecting waveguide matrix, matching oil, and microactuators. Switching is based on the movement of oil due to capillary pressure, which is controlled by the microactuator. The necessary switching conditions were calculated and the results showed that both the oil volume and the microactuator position must be controlled. A trial optical switch was fabricated to test the switching principle, and switching and self-holding were both confirmed. These results show the feasibility of a very small self-holding nn optical switch that uses a waveguide matrix and microactuators made by using microfabrication technologies.

We developed the computer calligraphy, that is, a computer formation of brush-written Kanji characters using calligraphic knowledge. The style of brush handwriting depends mainly on the way of using a writing brush. Brush writing skills include the direction of brush at the beginning, curvature and turning the brush, the brush-up at the termination point in a stroke. We make up the calligraphic knowledge base according to the above mentioned brush writing skills. For simulating real brush movement, we represent the brush contact form that is the brush shape on the writing plane as a brush-touch. The system can control the size and direction of this brush-touch during the brush simulation. The system simulates the real brush writing to move the brush-touch along the skeleton letter shape in the standard database. We get the brush written Kanji from the locus of the brush-touch movement. We can extend this system to the new on line training system for brush writing using the simulation of brushtouch movement modified by the pressure, speed and rotation of the writing brush, and the skeleton letters written by a learner from the tablet. This system is also useful for students learning how to write Japanese letters beautifully with brush.

The intelligent tutoring system (ITS) enables students to learn knowledge deductively. However, students often become passive, because the ITS takes the initiative in their learning process. Also their knowledge is often superficial, beacause they can not understand different kinds of knowledge due to their limited experience. This paper presents a virtual learning environment (VLE) for discovery learning. The VLE has been built with virtual reality (VR) technology, and supports the student's discovery learning activity and fosters his/her creativity and adaptability based on a broad range of experience by using the functions of VR such as interactivity, direct manipulation interface, walk-through, the function to change view point freely. Also, the VLE connects the explorative training by means of VR with guided education by the ITS. The student model in VLE evaluates the student's level of understanding and adjusts the training accordingly. We have built an operator training system for the training of control activities of electric power plant using the conception of the VLE. The purposes of this system are the following: to aid students to acquire adequate knowledge and skills, and to aid them to gain confidence and experience through their learning activities. The student model evaluates the student's level of understanding for experiential knowledge connected that of skills in VR with that of knowledge in ITS.

A formal system-level synthesis model for the concurrent object-oriented design of parallel computer systems, called Multi-token Object-oriented Bi-directional net (MOBnet), is proposed. The MOBnet model extends the standard Petri net by defining (1) multiple tokens to represent different kinds of synthesis control information, (2) object-oriented nodes (places) to denote the system parts under synthesis, and (3) bi-directional arcs to model the design completion check and synthesis rollback operations. In this paper, we first show that MOBnet can serve as a pre-fabrication design methodology analysis tool in ways such as class hierarchy construction, design specification comparison, reachability analysis, and concurrent process management and analysis. We then formally prove MOBnet to be a valid model for concurrent synthesis and give experimental application examples to verify. Finally, solution schemes for the design completion check and synthesis rollback problems are formally validated by analyzing the dynamic behavior of MOBnet, and experimentally illustrated through examples.

For object analysis and recognition, an original shape often needs to be described by using a small number of vertices. Polygonal approximation is one of the useful methods for the description. In this paper, we propose the curvature-based polygonal approximation (CBPA) method that is an application of the weighted polygonal approximation problem which minimizes the number of vertices of an approximate curve for a given error tolerance (the weighted minimum number problem). The CBPA method considers the curvature information of each vertex of an input curve as the weight of the vertex, and it can be executed in O(n2) time where n is the number of vertices of the input curve. Experimental results show that this method is effective even in the case when relatively few vertices are given as an original shape of a planar object, such as handwritten letters, figures (freehand curves) and wave-form data.