In this paper, an efficient one-way point-to-multipoint communication protocol (PTMP) is proposed. The PTM protocol is helpful to distribute information to many workstations simultaneously and correctly. The PTM protocol is designed for network channels with low error possibility. The PTM protocol utilizes broadcast for data distributing. Re-transmission request for lost packet is returned to the server, and acknowledgment for correctly received packets is not returned to the server. We have applied the protocol to the network presentation system. The network presentation system is intended to display same graphical images to multiple workstations simultaneously on an X window system. This presentation system is able to provide services for at least forty X servers simultaneously, the capacity is limited to X server performance, except for pixmap drawing. For the case of pixmap drawing, the system capacity is limited to the network bandwidth. To solve network bandwidth problem, we combined PTM protocol with the network presentation system. With PTM protocol, system performance is improved and the use of network bandwidth is lowered.

This paper discusses the problems in designing virtual-path (VP) networks and underlying transmission-path (TP) networks using the "self-sizing" capability. Self-sizing implies an autonomous adjustment mechanism for VP bandwidths based on traffic conditions observed in real time. The notion of "bandwidth demand" has been introduced to overcome some of the problems with VP bandwidth sizing, e.g., complex traffic statistics and diverse quality of service requirements. Using the bandwidth demand concept, a VP-bandwidth-sizing procedure is proposed in which real-time estimates of VP bandwidth demand and successive VP bandwidth allocation are jointly utilized. Next, TP bandwidth demand, including extra capacity to cover single-link failures, is defined and used to measure the congestion level of the TP. Finally, a TP provisioning method is proposed that uses TP "lifetime" analysis.

In the information engineering learning environment, there may be more than one solution to any given problem. We have developed CAMELOT using the Nominal Group Technique for group problem solving. This paper describes the collaborative learning system on the Internet using discussion model, the effectiveness of collaborative learning in modeling the entity-relationship diagram within the field of information engineering, and how to apply AI technologies such as rule-based reasoning and case-based reasoning to the pedagogical strategy. By using CAMELOT, each learner learns how to analyze through case studies and how to collaborate with his or her group in problem solving. As a result. We have found evidence for the effectiveness of collaborative learning, such as getting a deeper understanding by using CAMELOT than by individual learning, because they can reach better solutions through discussion, tips from other learners, examination of one another's individual solutions, and understanding alternative solutions using case-based reasoning.

This paper presents an analog 2-dimensional discrete cosine transform (2-D DCT) processor for focal-plane image compression. The on-chip analog 2-D DCT processor can process directly the analog signal of the CMOS image sensor. The analog-to-digital conversion (ADC) is preformed after the 2-D DCT, and this leads to efficient AD conversion of video signals. Most of the 2-D DCT coefficients can be digitized by a relatively low-resolution ADC or a zero detector. The quantization process after the 2-D DCT can be realized by the ADC at the same time. The 88-point analog 2-D DCT processor is designed by switched-capacitor (SC) coefficient multipliers and an SC analog memory based on 0.35µm CMOS technology. The 2-D DCT processor has sufficient precision, high processing speed, low power dissipation, and small silicon area. The resulting smart image sensor chips with data compression and digital transmission functions are useful for the high-speed image acquisition devices and portable digital video camera systems.

A new magnetostrictive thin-film cantilever actuator and a new thin-film walking mechanism were developed. The actuators were made of magnetostrictive amorphous Tb-Fe and Sm-Fe thin films, deposited on the opposite sides of a polyimide film substrate. These actuators need not power supply cables because they were remotely driven by external magnetic fields. The static deflection of a 3-mm-long cantilever actuator was as large as 100 µm at 300 Oe field. Moreover the application of ac resonant frequency field of the same intensity yielded deflection of above 500 µm. The walking mechanism ran as fast as in the order of cm/s. The forward and backward running were possible depending on the frequency of applied magnetic field. Such unique characteristics suggest that magnetostrictive thin-film actuators are useful in MEMS applications.

In recent years, and increasing number of studies have been reported regarding multimedia LANs that integrate voice, data and video communications. The Movable Boundary method has been suggested as a way to integrate circuit and packet switching. However, how this can be practically managed, especially for multimedia LANs, is not clear. Working under the assumption that an optical loop network in used as a multimedia LAN, we propose Hybrid Allocation as a new Movable Boundary method. Hybrid Allocation features traffic prediction for circuit switching calls, and timeslot allocation close to the boundary of circuit and packet switching areas. Evaluations of traffic simulation and network efficiency show it to be a promising architecture for integrating circuit and packet switching on a multimedia LAN.

Narrow-band ISDN services may experience nonstationary traffic conditions. Therefore, switch design should take account of these conditions. We propose new performance measures for switching systems and describe a traffic model, which is a mixture of stationary Poissonian traffic and momentarily focused traffic. On the basis of this model, performance measures are determined so as to satisfy grade of service requirements that are in effect during some short interval after the momentarily focused traffic enters the system. We also propose an overload control scheme that uses these new performance measures. Finally, we show practical and numerical examples for the performance measures and overload control scheme.

The design and engineering of new network intelligence platforms to accommodate the ever-changing and growing demands of customers, presents rich market opportunities and challenges tempered by concerns arising from the problematic experiences of similar system and network developments. As the telecommunications industry evolves, customers are increasingly coming to expect the perception of instantaneous access to service providers together with transparency to network failures. System performance dictates that response times need to be minimised, sufficient redundant capacity installed in case of failure and controls embedded within the design to manage the exceptional situations (such as media stimulated events) that continually threaten network integrity. Network design based on a 'top-down,' 'end-to-end' methodology plays a fundamental role in delivering solutions that meet customers' performance needs. It is necessary to consider service scenario mixes, service demand, physical network topology, signalling message flows, the mapping of functional entities to physical components, and routing as part of the network design process to ensure that performance requirements are met. The use of 'what-if' design tools is particularly relevant as part of this process. A challenging task faces the System Designer with the often conflicting goals of good performance and provision of service flexibility.

This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission such as Fiber-To-The-Home (FTTH). It enables to the handling of asynchronous burst-mode data. Without an external reference clock signal, it can make a quick extraction of clock signal from received data packets using a "gating-timing circuit" and a "burst PLL." The gating-timing circuit employs bit gating for a quick phase response, and the burst PLL employs frame gating for quick frequency adjustment to differences between packets and clock extraction. This circuit has a simple configuration without any external oscillators, which reduces both cost and power. A fabricated 0.5-µm CMOS IC exhibits instantaneous response within one bit for 156 Mb/s asynchronous data packets.

Significant traffic variations occur in telecommunication networks. This paper focuses on hour-to-hour traffic variations during 24 hours and investigates the possibility of using idle periods effectively by introducing non-realtime service at a discount rate. In order to provide non-realtime service, memory is placed at each telecom center. When immediate service is not available, messages of non-realtime calls are stored in the memory and served later when network resources are available. Realtime calls are served with preference. A basic model and a method of dimensioning the memory capacity are presented. The basic model is extended to the network model, and methods of designing a minimum cost network and pricing and profit issues are presented. The results for a basic model are verified by traffic simulation. Numerical examples are given to show the effectiveness of non-realtime service.

The progress of multimedia applications for education, research, social welfare and commerce is generating a lot of interest in the potential of a combination of satellite networking and Internet technology. The combination is particularly attractive as a low cost solution in regions which are large and sparsely populated. In 1991, aiming at networking the Pan-Pacific region, the PARTNERS (Pan-Pacific Regional Telecommunications Network Experiment and Research by Satellite) project was initiated. In this project, the major target was to construct a satellite-based network infrastructure to support education, research and so on in the Pan-Pacific region. As a part of PARTNERS the MEISEI-NET (Multimedia EducatIon System using satellite ETS-V and InterNET) project was started to evaluate the utility of satellite networking for education and reserch and, to investigate the feasibility of expanding the reach of the Internet using the PARTNERS infrastructure. MEISEI-NET focussed on (1) low start-up cost, (2) open access to the rich information resources on the Internet, (3) use of network to support education and research, and , (4) development and distribution of software for MEISEI-NET users. The construction of MEISEI-NET will be detailed followed by a report on its usage and the effects of this network. To support and manage MESEI-NET operations, we developed and deployed SNMP-based intelligent network management system. It offered fault detection and notification. This made the MEISEI-NET robust and practical despite of the satellite's (ETS-V) drift-problem. Students and researchers of universities from different countries participated in and benefited from MEISEI-NET until March 1996.

We propose an nn optical switch that is suitable for flexible and reliable optical access networks and for reconfigurable optical inter-module connections in large-scale processing systems. The switch consists of an intersecting waveguide matrix, matching oil, and microactuators. Switching is based on the movement of oil due to capillary pressure, which is controlled by the microactuator. The necessary switching conditions were calculated and the results showed that both the oil volume and the microactuator position must be controlled. A trial optical switch was fabricated to test the switching principle, and switching and self-holding were both confirmed. These results show the feasibility of a very small self-holding nn optical switch that uses a waveguide matrix and microactuators made by using microfabrication technologies.

This letter presents a realization of active current-mode resonator with complex coefficients using CCIIs. The resonator can be used for cascade or leapfrog configuration of high-order bandpass filters with complex coefficients. For realizing the resonators, only the grounded capacitors and the grounded resistors as passive elements are required, therfore the resonator is suitable for the integrated circuit realization. The letter shows that the response error of the proposed circuit caused by nonideality of active components is more easily compensated than that of voltage-mode counterpart. Experimental result is used for verifying the feasibility of the proposed resonator.

Recently, various systems based on agent model architecture have been developed. In these systems, 'agents' with their own goals and functions are embedded, and perform their own tasks through collaboration among them by communication to achieve a goal as the system requires. Using this agent model for the construction of educational systems, adaptive configuration of the system is achieved. The purpose of this study is to propose a methodology for the design of an educational system based on agent model architecture. This paper describes the configuration of the agent model and the communication language and protocol used to represent collaboration among the agents necessary for performing a cooperative task. Moreover, we explain how to organize these agents as an educational system. As a case to show the organization of agents, we discuss the configuration of an intelligent learning environment to support C shell programming in UNIX and explain the collaborative behavior of embedded agents.

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.

Many efforts are currently underway to design wideband mobile communication systems. In this letter, we clarify the received signal level characteristics for wideband mobile radio channels in line-of-sight (LOS) microcells. We conduct several urban-area field experiments to measure the received signal levels for various receiver bandwidths from 300 kHz to 30 MHz and the power delay profile. The experimental results show that the fading depth of the received signal decreases as the normalized rms delay spread, defined as the product of receiver bandwidth and rms delay spread, increases. These results are useful in designing wideband microcell systems for urban areas.

This paper presents an 8-bit 200M-sample/s (Ms/s) analog-to-digital converter (ADC) applicable to liquid crystal display (LCD) driver systems. The ADC features such circuit techniques as a low-power and high-speed comparator, an open-loop sample-and-hold amplifier with a 3.4-ns acquisition time, a fully differential two step architecture, and a replica circuit. It is fabricated with a 0.8µm BiCMOS process onto an area of only 12mm2 and it dissipates 500mW from a single-5.2V power supply.

We show that the truth of a prenex normal form Presburger sentence bounded only by existential quantifiers (or an EPP-sentence) involving two variables can be decided in deterministic polynomial time. Specifically, an upper bound of the computation for the decision is O(n3u), where n is the number of atoms of the EPP-sentence, and u is the largest absolute value of all coefficients in the EPP-sentence. In the analysis for the upper bound, the random access machine is assumed for the machine model. Additionally, a uniform cost criterion is assumed. Deciding the truth of an EPP-sentence is an NP-complete problem, when the number of variables is not fixed. Furthermore, whether the truth of an EPP-sentence involving two or more variables can be decided in deterministic polynomial time, when the number of variables is fixed, or not has remained an open problem. We previously proposed a procedure for quickly deciding the truth of an EPP-sentence on the basis of a suggestion by D.C.Cooper. We found the upper bound by analyzing the decision procedure. The procedure can be applied to both automated correctness proof of specification in various design fields and detection of infeasible paths in a program. In the procedure, a matrix denoting coefficients of the variables in the EPP-sentence is triangulated.

A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.

A sequence of nonnegative integers s=(S1, s2, , sn) is a score sequence of an r-tournament if, for some positive integer r, ther is a directed graph with vertices v1, v2, , vn such that deg+(vj)=sj and deg-(vj)=r(n-1) -sj for each j=1, 2, , n. The score sequence problem of an r-tournament is: Given some positive integer r and a sequence of nonnegative integers, determine whether it is a score sequence of an r-tournament or not. In this paper, we consider several variations of the score sequence problem of an r-tournament, and give efficient algorithms.