This paper evaluates the performance of DS/CDMA with diversity coding and multiuser interference (MUI) cancellation in fading multipath channel. The diversity technique considered in this paper, is different from the conventional scheme and transmits different information over different channels. It is shown that, this diversity scheme performs better than conventional diversity scheme, and when combined with MUI cancellation provides significant performance improvement. Effects of partial band jamming on the system are also considered.

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

In this letter, we propose a blind adaptive receiver with nonlinear structure for DS/CDMA communication systems. The proposed receiver requires the signature waveform and timing for only the desired user. It is shown that the blind adaptation is equivalent to the adaptation with the training signal and the function to be minimized has no local minima.

A generalized Reed-Muller expression (GRM) is obtained by negating some of the literals in a positive polarity Reed-Muller expression (PPRM). There are at most 2(n2)^(n-1) different GRMs for an n-variable function. A minimum GRM is one with the fewest products. This paper presents certain properties and an exact minimization algorithm for GRMs. The minimization algorithm uses binary decision diagrams. Up to five variables, all the representative functions of NP-equivalence classes were generated and minimized. Tables compare the number of products necessary to represent four-and five-variable functions for four classes of expressions: PPRMs, FPRMs, GRMs and SOPs. GRMs require, on the average, fewer products than sum-of-products expressions (SOPs), and have easily testable realizations.

In order to highlight a rapid progress attained in the field of millimeter waves in Japan, this paper describes several key topics including transistors, integrated circuits, planar antennas, millimeter wave photonics, and others.

In this paper, we consider the protein structure alignment problem, which is a very important problem in molecular biology. Since an outline of protein structure is represented by a sequence of points in three-dimensional space, this problem is defined as the following geometric pattern matching problem: given two point sequences P and Q in three-dimensions and a real number δ > 0, find a maximum-cardinality set of point pairs such that the distance between each pair is at most δ under the condition that any translation and rotation can be applied to P. Since it is very difficult to solve this problem exactly, we consider algorithms that solve it approximately. We propose three algorithms: BASICALIGN, RANDALIGN and FRAGALIGN whose worst case time complexities are O(n8), O((n7/k3) polylog(n)) and O(n4) respectively, where n denotes the size of larger input structure and k denotes the minimum size of the alignment to be obtained. All of these have the following common framework: a series of initial superpositions are computed; for each of such superpositions, a rough alignment is first computed using a dynamic programming technique, and then it is refined through an iterative improvement procedure which also uses dynamic programming; the best alignment among them is selected as an output. The difference among three algorithms lies in the methods of finding initial superpositions. BASICALIGN, RANDALIGN and FRAGALIGN use exhaustive search, random sampling technique and fragment-based search, respectively. We prove guaranteed approximation ratios (in the sense of distances between point pairs) for theoretical versions of BASICALIGN and RANDALIGN. Practical versions of RANDALIGN and FRAGALIGN were implemented and compared with a previous algorithm using real protein structure data. The experimental results show that FRAGALIGN is best among them and it outputs good alignments quickly.

A direct-mapped cache takes less time for accessing data than a set-associative cache because the time needed for selecting a cache line among the set is not necessary. The hit ratio of a direct-mapped cache, however, is lower due to the conflict misses caused by mapping multiple addresses to the same cache line. Addressing cache memory by virtual addresses reduces the cache access time by eliminating the time needed for address translation. The synonym problem in virtual cache necessitates an additional field in the cache tag to denote the process to which cache line belongs. In this paper, we propose a new virtual cache architecture whose average access time is almost the same as the direct-mapped caches while the hit ratio is the same as the set-associative cashes. A victim for cache replacement is selected from those that belong to a process which is most remote from being scheduled. The entire cache memory is divided into n banks, and each process is assigned to a bank. Then, each process runs on the assigned bank, and the cache behaves like a direct-mapped cache. Trace-driven simulations confirm that the new scheme removes almost as many conflict misses as does the set-associative cache, while cache access time is similar to a direct-mapped cache.

The quality of a modular software system depends on the reliabilities of the software modules and the software operational profile. When the software is designed for multiple customers having different operational profiles, different customers may experience different software quality. It is important to ensure that no customer will suffer from a poor software quality. In this paper, we formulate and solve three reliability allocation problems for modular software system designed for multiple customers. In these reliability allocation problems, we consider the software operational profile of every customer while fulfilling such practical constraints as cost budget and software quality requirement. The numerical results show that when the operational profiles of the customers are more skewed, it is more beneficial to take their operational profiles into account.

This paper describes a millimeter-wave (MMW) transmission system over fiber-optic links applicable for high-speed mobile communications. The system design is presented considering both the MMW radio link and fiber-optic link. To prove the capability of the MMW fiber-optic link, an experimental system has been constructed. The results of in-door transmission experiments showed that this system could be capable of transmitting 118 Mbps digital signals with a BER of less than 10-6. The developed system is easily applicable to a wireless access system which can connect subscribers with a broadband optical fiber network.

An important aspect of traffic safety is the development of aids that extend the driver's time and motion perception. One promising candidate is the compact, lightweight millimeter-wave FM-CW radar now being widely studied. Although the homodyne FM-CW radar is well known form its simplicity, it has a relatively low S/N ratio. This paper describes the principles behind our newly-developed heterodyne FM-CW radar and it's evaluation results. The heterodyne FM-CE radar generates sidebands by switching a front-end amplifier and also uses the heterodyne detection technique for gaining sensor sensitivity. The heterodyne FM-CW radar's signal to noise ratio was 19.5 dB better than previously designed homodyne FM-CW radar.

Because 60 GHz frequency band has been allotted for the research and development purpose of millimeter wave systems in Japan, various circuit components and systems have been fabricated by using printed transmission lines. The NRD guide (nonradiative dielectric waveguide) is another candidate as a transmission medium for millimeter wave integrated circuit applications since its performance has been shown to be excellent in this frequency band. This paper is concerned with the development of a 60 GHz digital transceiver for millimeter wave LAN use based on NRD guide technologies. The trans-ceiver consists of frequency stabilized Gunn oscillator, circulator, PIN diode modulator, balanced mixer, directional coupler and transmitting and receiving pyramidal horn antennas. The notable advantages of the circuit components are the high reliability of the Gunn oscillator, the wide bandwidth of the circulator, and the high frequency operation of the PIN diode modulator beyond 100 Mbps. Interference between transmitted and received signals, which must be caused by coupling between transmitting and receiving antennas, is eliminated by simple techniques such as introducing filters in the base band and IF circuits. By using NRD guide digital transceivers, both-way data transmission between two computers can be achieved simultaneously and a 60 GHz wireless LAN system has been developed successfully.

In outdoor fields such as construction, mining and agriculture, there is an increasing demand for autonomous vehicles to reduce labor costs. Also, a positioning system is one key technology required for autonomous vehicle systems. For the purpose of expanding the potential of millimeter-wave applications, we have developed a positioning system in the 77-79 GHz frequency band, using the hyperbolic radio navigation method. This system operates in a restricted area with a radius of about a few hundred meters. A spread spectrum with a PN code is used as the ranging signals. We realized about 0.1 m in positioning accuracy.

A current controlled CMOS output driver was designed by using a temperature-insensitive reference current generator. It eliminates the need for overdesign of the driver transistor size to meet the delay specification at high temperature. Comparison with the conventional CMOS output driver with the same transistor size showed that the ground bounce noise was reduced by 2.5 times and the delay time was increased by 1.4 times, at 25 for 50pF load. The temperature variations of the DC pull-up and pull-down currents of the new output driver were 4% within the temperature range from -15 to 125 compared to the variations of 40 and 60% for pull-up and pull-down respectively for the conventional output driver. The temperature insensitivity of the reference current generator was achieved by multiplying two current components. one which is proportional to mobility and the other which is inversely proportional to mobility, by using a CMOS square root circuit. The temperature variation of the DC output current of the reference current generator alone was 0.77% within the entire temperature range from -15 to 125.

To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.

Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

We propose a novel feeding circuit for a 30 GHz planar multibeam antenna applied to high-speed wireless communication systems. The feeding circuit is a bi-layer 8-port Butler matrix constructed with phase adjusted slot-coupled hybrids and branch-line hybrids. The new circuit configuration eliminates troublesome vias and line crossings, so it can be manufactured by traditional photolithograph. The feeding circuit is designed by using the spectral domain moment method considering bonding film effects. A prototype of a multibeam antenna which has seven pencil-beams with 10 beamwidths is manufactured and tested; the beam scan angle error is less than 3 at 30 GHz.

This paper presents a new method for the selftuning control of nonminimum phase discrete-time stochastic systems using approximate inverse systems obtained from the leastsquares approximation. Using this approximate inverse system the gain response of the system can be made approximately unit and phase response exactly zero. We show how unstable polezero cancellations can be avoided. This approximate inverse system can be used in the same manner for both minimum and nonminimum phase systems. Moreover, the degrees of the controller polynomials do not depend on the approximate inverse system. We just need an extra FIR filter in the feedforward path.

In this paper stochastic aradient adaptive filters using the Sign or Sign-Sign Algorithm are analyzed based upon general assumptions on the reference signal, additive noise and particularly jointly distributed tap errors. A set of difference equations for calculating the convergence process of the mean and covariance of the tap errors is derived with integrals involving characteristic function and its derivative of the tap error distribution. Examples of echo canceller convergence with jointly Gaussian distributed tap errors show an excellent agreement between the empirical results and the theory.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.