The throughput performance of the non-persistent carrier sense spread spectrum with overload detection (NP-CSSS/OD) protocol is analysed and compared with that of the conventional non-persistent and one-persistent carrier sense multiple access with collision detection (NP-CSMA/CD and 1P-CSMA/CD) and the one-persistent carrier sense spread spectrum with overload detection (1P-CSSS/OD) protocols. We also introduced utilization measurements and did some performance comparisons between these protocols. At high offered loads, the NP-CSSS/OD protocol is found to offer the best throughput and utilization performances amongst them.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

Conceptual graph formalism is a knowledge representation language in AI based on a graphical form of logic. Although logic is the basis of the conceptual graph theory, there is a strongly felt absence of a formal treatment of conceptual graphs as a logic programming language. In this paper, we develop the notion of a conceptual graph program as a kind of graph-based order-sorted logic program. First, we define the syntax of the conceptual graph program by specifying its major syntactic elements. Then, we develop a kind of model theoretic semantics and fixpoint semantics of the conceptual graph program. Finally, we show that the two types of semantics coincide for the conceptual graph programs.

Schnorr's identification scheme is the most efficient and simplest scheme based on the discrete logarithm problem. Unfortunately, Schnorr's scheme is not provably secure, i.e., the security has not been proven to be reducible to well defined intractable problems. Two works have already succeeded to construct provably secure variants of Schnorr's scheme. They have been constructed with a common approach, i.e., by modifying the formula to compute the public key so that each public key has multiple secret keys. These multiple secret keys seem to be essential for their provable security, but also give rise to a penalty in their efficiency. In this paper, we describe a new approach to constructing a provably secure variant, where we never modify the formula, and show that with our approach, we can construct a new efficient provably secure scheme.

This paper proposes a new class of error locating codes which corrects random single-bit errors and indicates a location of an erroneous b-bit byte which includes e-bit errors, where 2 e b, called SECSe/bEL codes. This type of codes is very suitable for an application to memory systems constructed from byte-organized memory chips because this corrects random single-bit errors induced by soft-errors and also indicates the position of the faulty memory chips. This paper also gives a construction method of the proposed codes using tensor product of the two codes, i.e., the single b-bit byte error correcting codes and the single-bit error correcting and e-bit error detecting codes. This clarifies lower bounds and error control capabilities of the proposed codes.

To connect among many radio base stations by using optical fiber bus link in microcellular system, subcarrier multiplexing (SCM) is excellent in simplicity and flexibility. But performance degradation due to optical beat noises is severe problem. To solve this problems, this paper proposes a new type of intercell connection bus fiber-optic link (ICBL) using time division multiplexing, called TDM-ICBL. This paper also analyzes transmission performance of TDM-ICBL theoretically and compares with SCM-ICBL. The analysis clarifies that while the number of RBSs connected to SCM-ICBL is severely restricted by beat noises, TDM-ICBL is more useful than SCM-ICBL when there are many number of connected RBSs.

In this paper we propose a two-stage address coding scheme to transmit two data symbols at once within a frame in a MFSK/FH-CDMA system. We compare it with the conventional system using single-stage address coding. Assumed that the address codes of all users are known in the receiver. A multiuser detection scheme is applied and the performance is evaluated by computer simulations to show the improvement in bit error rate (BER) compairing to the conventional system. We also investigate the performance of error-correcting coding and decoding in the two-stage address coded MFSK/FH-CDMA system. An erasure decoding scheme is modified for the two-stage address coded system and is utilized to improve spectral efficiency or to increase user capacity in the MFSK/FH-CDMA system. Finally, we investigate a hybrid scheme of combining the multi-user detection scheme and the error-correcting decoding scheme for the two-stage address coded MFSK/FH-CDMA system. The performance is evaluated by computer simulations.

This paper investigates the error correcting capabilities of concatenated codes employing algebraic geometry codes as outer codes and time-varying randomly selected inner codes, used on discrete memoryless channels with maximum likelihood decoding. It is proved that Gallager's random coding error exponent can be obtained for all rates by such codes. Further, it is clarified that the error exponent arbitrarily close to Gallager's can be obtained for almost all random selections of inner codes with a properly chosen code length, provided that the length of the outer code is sufficiently large. For a class of regular channels, the result is also valid for linear concatenated codes, and Gallager's expurgated error exponent can be asymptotically obtained for all rates.

When bit error probability of a trellis-coded modulation (TCM) scheme becomes very small, it is almost impossible to evaluate it by an ordinary Monte-Carlo simulation method. Importance sampling is a technique of reducing the number of simulation samples required. The reduction is attained by modifying the noise to produce more errors. The low error rate can be effectively estimated by applying importance sampling. Each simulation run simulates a single error event, and importance sampling is used to make the error events more frequent. The previous design method of the probability density function in importance sampling is not suitable for the TCM scheme on an additive non-Gaussian noise channel. The main problem is how to design the probability density function of the noise used in the simulation. We propose a new design method of the simulation probability density function related to the Bhattacharyya bound. It is reduced to the same simulation probability density function of the old method when the noise is additive white Gaussian. By using the proposed method for an additive non-Gaussian noise, the reduction of simulation time is about 1/170 at bit error rate of 106 if the overhead of the calculation of the Bhattacharyya bound is ignored. Under the same condition, the reduction of the simulation time by the proposed method is 1/65 of the ordinary Monte-Carlo method even if we take the overhead for importance sampling into account.

This paper discusses linear cryptanalysis of LOKI89, LOKI91 and s2DES. Our computer program based on Matsui's search algorithm has completely determined their best linear approximate equations, which tell us applicability of linear cryptanalysis to each cryptosystem. As a result, LOKI89 and LOKI91 are resistant to linear cryptanalysis from the viewpoint of the best linear approximate probability, whereas s2DES is breakable by a known-plaintext attack faster than an exhaustive key search. Moreover, our search program, which is also applicable to differential cryptanalysis, has derived their best differential characteristics as well. These values give a complete proof that characteristics found by Knudsen are actully best.

A quasi-synchronous (QS) code division multiple access (CDMA) system is proposed for mobile communications. In the proposed method, which uses the time division duplex (TDD) mode of transmission, a mobile receiver can measure propagation delay changes. It then accordingly adjusts its transmission time so its signal can arrive at base station synchronously with other mobile units. A simple control unit is used at the mobile unit in order to reduce any error due to the propagation delay changes. The system operates as follows. At the start of a call, a mobile unit is quasi-synchronised through feedback control from the base station. The mobile unit then maintains synchronous status without any further base station feedback. The degree of the quasi-synchronous accuracy is determined by a clock in mobile units. This paper shows performance results based on using a clock rate of ten times faster than the spreading rate. Orthogonal codes are used for spreading the signals. The results demonstrate that the reverse link CDMA multiuser interference is to a great degree removed.

The influence of cochannel, adjacent channel and intermodulation constraints on the capacity of the frequency band in the dynamic channel allocation problem is estimated. Algorithms including a backtracking phase with partial reassignment of currently assigned requirements are proposed. Numerical examples show a strong possibility of a 20% capacity improvement compared to the conventional strategies.

Intelligent Tutoring Systems (ITS) represents a wide class of computer based tutoring systems, designed with an extensive use of the technology of modern Artificial Intelligence. Successful applications of various expert systems and other knowledge based systems of AI gave rise to a new wave of interests to ITS. Yet, many authors conclude that practically valuable achievements of ITS are rather modest despite the relatively long history of attempts to use knowledge based systems for tutoring. It is advocated in this paper that some basic obstacles for designing really successful ITS are due to the lack of well understood and sound models of the education process. The paper proposes to overcome these problems by borrowing the required models from AI and adjacent fields. In particular, the concept of Learning Levels from AI might be very useful both for giving a valuable retrospective analysis of computer based tutoring and for suggestion of some perspective directions in the field of ITS.

The background concepts and methodologies of the knowledge-based program understander ALPUS is discussed. ALPUS understands user's buggy Pascal programs using four kinds of programming knowledge: the knowledge on algorithms, programming techniques, the Pascal language, and logical bugs. The knowledge on algorithms, the key knowledge, is represented in a form of hierarchical data structure called Hierarchical Procedure Graph (HPG). In HPG each node represents a chunk of operations called process," which is consisted of sub-processes. The other knowledge is maintained as independent knowledge bases and linked to associated processes of the HPG. The knowledge about bugs acquired by cognitive experiment is grouped into three categories: bugs on algorithms, programming techniques, and the Pascal language, and connected to associated elements of programming knowledge respectively. ALPUS tries to understand user's buggy programs, detects logical bugs, infers user's intentions, and gives advices for fixing bugs. Program understanding is achieved by three steps: normalization, variable identification, and process and technique identification. Normalization results in improving flexibility of understanding. Variable, process and technique identifications are achieved by knowledge-based pattern matching. Intentions are inferred by means of information attached to buggy patterns. The result of comprehension is reported to a user (i.e., student). Experimental results using Quicksort programs written by students show that the HPG formalism is quite powerful in understanding algorithm-oriented programs. The ALPUS's way of program comprehension is useful in the situation of programming education in an intermediate class of an engineering school. The ALPUS system is a subsystem of the intelligent programming environment INTELLITUTOR for learning programming, which was implemented in the frame-based knowledge engineering environment ZERO on a UNIX workstation.

This paper proposes a novel phase ambiguity resolver with combining a very low power Viterbi decoder employing a scarce state transition scheme to realize cost effective receivers for the PCM sound broadcasting satellite service. The theoretical analyses on phase decision performance show that the proposed resolver achieves the symbol-by-symbol phase detection and decides correctly phases of the demodulated data even if the bit error probability of 710-2. The resolver also reduces the phase decision time to below 1/1000 of that of the conventional resolver. Furthermore, experimental results of the power consumption estimate that the prototype Viterbi decoder consumes only 60mW at the data rate of 24.576Mbit/s.

This paper presents the fabrication and evaluation of a 60 GHz fully integrated MMIC one-chip receiver based on pseudomorphic InGaP/InGaAs/GaAs HEMT technology. The receiver consists of two 2-stage low-noise amplifiers (LNAs), a single-balanced active-gate mixer, a local oscillator (LO), and a buffer amplifier for the LO. The receiver has a conversion gain of greater than 17 dB from 60.2 GHz to 62.3 GHz, and the maximum conversion gain is 20 dB at 62.2 GHz. The noise figure of receiver is less than 6 dB in the IF range between 100 MHz and 1 GHz for a 61.536 GHz LO frequency, and the minimum noise figure is 4.9 dB at 1 GHz IF.

The effect of an optical hard-limiter on the performance of direct-detection optical synchronous code-division multiple-access (CDMA) systems with M-ary pulse position modulation (PPM) signaling is analyzed. Moreover, the effect of the error correction coding on the performance of direct-detection optical synchronous CDMA systems with PPM signaling is analyzed: Reed-Solomon (RS) codes and convolutional codes (CC's) with soft-decision Viterbi decoding are employed. We analyze the performance under the assumption of Poisson shot noise model for the receiver photodetector and the noise due to the detector dark currents is considered. We analyze the performance under average power and bit rate constraints. Our results show that the optical hard-limiter is not effective for improving the performance of the optical CDMA systems with PPM signaling. Moreover, RS codes are shown to be more effective than CC's with soft-decision Viterbi decoding to reduce an asymptotic floor to the error probability of the system with large M, while CC's with soft-decision Viterbi decoding is more effective than RS codes for the system with small M. Furthermore, we show that as the code rate of the error correction code increases, the required average energy to achieve the bit error probability Pb105 for the RS coded PPM/CDMA system appreciably increases compared with that for the convolutional coded PPM/CDMA system when M16.

A 0.5 µm CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell; high speed, compiled type metallized and diffused RAMs; PLL (Phase Locked Loop); and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.

This paper describes 950 GHz power performance of double-doped AlGaAs/InGaAs/AlGaAs heterojunction field-effect transistors (HJFET) operated at a drain bias voltage ranging from 2.5 to 3.5 V. The developed 1.0 µm gatelength HJFET exhibited a maximum drain current (Imax) of 500 mA/mm, a transconductance (gm) of 300 mS/mm, and a gate-to-drain breakdown voltage of 11 V. Operated at 3.0 V, a 17.5 mm gate periphery HJFET showed 1.4 W Pout and -50.3 dBc adjacent channel leakage power at a 50 kHz off-carrier frequency from 950 MHz with 50% PAE. Harmonic balance simulations revealed that the flat gm characteristics of the HJFET with respect to gate bias voltage are effective to suppress intermodulation distortion under large signal operation. The developed HJFET has great potential for small-sized digital cellular power applications operated at a low DC supply voltage.

The use of existing metallic local line facilities is being studied for providing "video on demand (VOD)" services to residential subscribers across asymmetric digital subscriber lines (ADSL). ADSL carries a high-rate channel in the downstream direction from a central office (CO) to the subscriber, and a low-rate channel in both directions on an existing 2-wire pair. Audio and video signals are compressed by the moving picture experts group's standardized algorithms (MPEG 1 and MPEG 2), and delivered to the subscriber in the high-rate channel. Control (demand and response) signals are transceived in the low-rate channel. This paper presents the line length coverage of ADSL systems given the environment of NTT's local networks. The bit rates in the downstream and upstream directions are assumed to be 1.6-9.2Mbit/s and 24kbit/s, respectively. Two types of ADSL systems are considered: transceiving ADSL signals using the plain old telephone service (POTS) line or the basic rate access (BRA; 320 kbaud ping-pong transmission system) line on the same 2-wire pair. 16-QAM, 32-QAM and 64-QAM are compared as transmission schemes. Intra-system crosstalk interference (interference between identical transmission systems) and inter-system crosstalk interference (interference between different transmission systems) with the existing digital subscriber lines (DSL) are estimated. It is shown that the inter-system crosstalk interference with BRA is most stringent, and ADSL with 16-QAM yields the best performance in NTT's local networks. This paper concludes that realizing ADSL with 16-QAM can achieve channel capacities of up to 9.2Mbit/s for fiber-in-the-feeder (FITF) access systems, but the possibility of applying ADSL to direct access systems is remote except for a restricted short haul use. Some comparisons regarding American local networks are also described.