Threshold voltage shift in high frequency operation of 0.3µm and 0.35µm gate SOI CMOS is experimentally studied, using supply current measurement of inverter chains as test structures. The threshold voltage shift is obtained from the measurement of the leak currents in DC and high frequency condition. For a large supply voltage the electron-hole generation current becomes dominant, resulting in lowered threshold voltage, while the threshold voltage becomes higher than DC case for a low supply voltage. A reasonable relation of the threshold voltage shift and average electric field in the channel is obtained in this study. This method will be useful as a measure of "substrate current" for floating body SOI CMOS.

ElectroStatic Discharge (ESD) testing of integrated circuits subjects circuit elements to very high currents for short periods of time. A modified Transmission Line Pulse (TLP) measurement system for characterizing transistors and other circuit elements under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure leakage. For the TLP system to yield useful information test structures are needed which vary the important design parameters for the circuit elements. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.

Effects of field edge steps on characteristics of MOSFETs with tungsten polycide stacked gate electrodes patterned by KrF excimer laser lithography was studied through an electrical gate length measurement technique. Sheet resistance of the gate electrodes on the field oxide, on the active region and across the field edge steps was determined from the relationship between gate conductance and designed gate linewidth. The sheet resistance of the gate electrode across the field edge steps was larger than that on the flat regions. Effects of field edge steps on gate linewidth variation were evaluated by SEM observations and electrical measurements. Distribution of gate linewidth in a wafer was measured by the MOSFET test structures with the linewidth down to sub-quarter micron. Gate linewidth variation near the field edge steps was found to influence the short channel MOSFET characteristics.

A test structure has been developed with very low-level current measurement technique and is used to evaluate a very small change of leakage current caused by the trapping and detrapping of electrons or holes. The present technique realizes detection of very low levels of leakage current (minimum detectable current is 510-17 A), which is necessary in the course of evaluating gate oxides. This technique is very useful for the evaluation of retention characteristics and stress induced degradation of gate oxides.

In general, a time-limited signal such as a single sinusoidal waveform framed by a frame period T can be utilized for conveying a multi-level symbol in data transmission. If such a signal is analyzed by the conventional DFT (Discrete Fourier Transform) analysis, the infinite number of frequency components with frequency spacing fD = T1 is needed. This limits the accuracy with which the original frequency of the unframed sinusoidal waverform can be identified. It is especially difficult to identify two similar framed sinusoids whose frequency spacing is narrower than fD. An analytical principle for time-limited signals is therefore proposed by introducing the concept of an Extended Frame into DFT. Waveform analysis more accurate than DFT is achieved by taking into account multiple correlations between extended frames made of an input frame signal and the element frequency components corresponding to the length of each extended frame. In this approach, it is possible to use arbitrary element frequency spacing less than fD. It also allows an element frequency to be selected as a real number times of fD, rather than as an integer times of fD that is used for DFT. With this analyzing mechanism, it is verified that an input frame signal with only the frequency components which coincide with any of the element frequencies can be exactly analyzed. The disturbance caused by the input white noise is examined. As a result, it is found that the superior noise suppression function is achieved by this method over a conventional matched filter. In addition, the error caused by using a finite number of element frequencies and the A/D conversion accuracy required for sampling an input signal are examined, and it is shown that these factors need not impede practical implementation. For this reason, this principle is useful for multi-ary transmission systems, noise tolerant receivers, or systems requiring precise filtering of time limited waveforms.

Throughout the paper, the proper operating of the self-routing principle in 2-D shuffle multistage interconnection networks (MINs) is analysed. (The notation 1-D MIN and 2-D MIN is applied for a MIN which interconnects 1-D and 2-D data, respectively.) Two different methods for self-routing in 2-D shuffle MINs are presented: (1) The application of self-routing in 1-D MINs by a switch-pattern preserving transformation of 1-D shuffle stages into 2-D shuffle stages (and vice versa) and (2) the general concept of self-routing in 2-D shuffle MINs based on self-routing with regard to each coordinate which is the original contribution of the paper. Several examples are provided which make the various problems transparent.

Distributed shared memory is an attractive option for realizing functionally distributed computing in a wide area distributed environment, because of its simplicity and flexibility in software programming. However, up till now, distributed shared memory has mainly been studied in a local environment. In a widely distributed environment, latency of communication greatly affects system performance. Moreover, bandwidth of networks available in a wide area is dramatically increasing recently. DSM architecture using high performance networks must be different from the case of low speed networks being used. In this paper, distributed shared memory models in a widely distributed environment are discussed and evaluated. First, existing distributed shared memory models are examined: They are shared virtual memory and replicated shared memory. Next, an improved replicated shared memory model, which uses internal machine memory, is proposed. In this model, we assume the existence of a seamless, multi-cast wide area network infrastructure - for example, an ATM network. A prototype of this model using multi-thread programming have been implemented on multi-CPU SPARCstations and an ATM-LAN. These DSM models are compared with SCRAMNetTM, whose mechanism is based on replicated shared memory. Results from this evaluation show the superiority of the replicated shared memory compared to shared virtual memory when the length of the network is large. While replicated shared memory using external memory is influenced by the ratio of local and global accesses, replicated shared memory using internal machine memory is suitable for a wide variety of cases. The replicated shared memory model is considered to be suitable particularly for applications which impose real time operation in a widely distributed environment, since some latency hiding techniques such as context switching or data prefetching are not effective for real time demands.

In this paper, we formulate and solve a discrete-time queueing problem that has two potential applications: ATM multiplexers and DQDB networks. We first consider the modeling of an ATM multiplexer. The object of the analysis is a periodic traffic stream (CBR traffic), which is one of the inputs to the multiplexer. As in previous works of the subject, we consider a memoryless background traffic input. Here, in addition to this background traffic, we take into account the influence of a high-priority traffic, which is time-correlated and requires expedited service. We analyze the influence of these two types of traffic on the statistics of the interdeparture time (jitter process) and the delay of the periodic traffic stream. We obtain their distributions in a form of z-transforms, and from these we derive closed form expressions for the average delay and the variance of the interdeparture time. Our results show that the delay and jitter are very sensitive to the burstiness of the high priority traffic arrival process. We next apply our analytical modeling to a DQDB network when some of its stations are driven by CBR sources. We can obtain interesting results concerning the influence of the physical location of a DQDB station on the jitter.

This paper proposes an integrated interference suppression scheme which realizes interference-resistant satellite digital signal transmission systems. It employs a notch filter in the receiving side to suppress the co-channel interference (CCI) signal. Moreover, the proposed scheme employs an adaptive equalizer combined with a forward error correction (FEC) scheme to improve the Pe (probability of error) performance degradation due to the inter-symbol interference caused by notch filtering of the desired signal. In the typical frequency modulation (FM) CCI environment with a BWi/FN of 2.3 (BWi: interference signal required bandwidth, fN: one half the Nyquist bandwidth of the desired signal), a Δf / fN of 1.05 (Δf: interference frequency offset) and a D/U of 3 dB (desired to undesired (interference) signal power ratio), the proposed scheme improves the required Eb/NO by 1.5 dB at a Pe of 10-4 compared to that without an adaptive equalizer.

Existing edge detection methods provide unsatisfactory results when contrast changes largely within an image due to non-uniform illumination. Koch et al. developed an energy function based upon the Hopfield neural network, whose coefficients were fixed by trial and error, and remain constant for the entire image, irrespective of the differences in intensity level. This paper presents an improved edge detection method for non-uniformly illuminated images. We propose that the energy function coefficients for an image with inconsistent illumination should not remain fixed, rather should vary as a second-order function of the intensity differences between pixels, and actually use a schedule of changing coefficients. The results, compared with those of existing methods, suggest a better strategy for edge detection depending upon both the dynamic range of the original image pixel values as well as their contrast.

The degradation of I-V characteristics under constant emitter-base reverse voltage stress in advanced self-aligned bipolar transistors was analyzed. Experimental analyses have been taken the stress field effect into account when predicting hot-carrier degradation. These analyses showed that base current starts to increase when the reverse voltage stress is about 3 V. The dependence of the base current change on reverse voltages of more than 3 V was also investigated experimentally, and equations expressing hot-carrier degradation in terms of the exponential dependence of excess base current on both reverse stress voltage and stress-enhancing voltage related to emitter-base breakdown voltage were derived.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

The electrical characteristics of sealed CMOSFETs with gates crossing sources/drains at 90 and 45 are experimentally investigated using test devices fabricated by an n-well CMOS process with trench isolation. Gain factors of surface-channel 90 and 45 n-MOSFETs can be estimated by a simple correction theory based on the combination of a center MOSFET and two edge MOSFETs. However, relatively large departures from the theory are observed in buried-channel 90 and 45 p-MOSFETs with widths less than the channel length. The difference between n- and p-MOSFETs is mainly due to the channel type. Other basic device parameters such as saturation drain currents, threshold voltages, subthreshold swings, maximum substrate currents and substrate-voltage dependence of threshold voltages are also measured and qualitatively explained.

This letter presents a new design method for approximate inverse systems using all-pass networks. The efficacy of approximate inverse systems for input and parameter estimation of nonminimum phase systems is well recognized. in the previous methods, only time domain design of FIR (finite impulse response) type approximate inverse systems were considered. Here, we demonstrate that IIR (infinite impulse response) type approximate inverse systems outperform the previous methods. A nonlinear optimization technique is adopted for designing the proposed system in the frequency domain. Numerical examples are also presented to show the effectiveness of the proposed method.

This letter describes an efficient and economical method for dropping optical fiber to residential premises in which several fiber ribbons in a distribution cable are assigned to one dropping point. The optical fiber cables for dropping, which contain mono-coated fibers, are then aerially installed between several poles from this point during initial construction. One or two fibers in a cable are then branched and dropped to a subscriber when the demand arises. When an optical drop wire stranded cable is used as the optical fiber cable for dropping, the above method can be employed without the need for a fiber joint in the dropping portion. The tube stranding pitch of this cable is investigated theoretically and experimentally, and the cable is manufactured based on the results. The transmission characteristics of the cable are confirmed to be stable.

Shortened prime codes (SPR-codes) are presented, which can maintain the fixed code weight for any arbitrary number of codewords while still preserve the same cross and auto-correlation constraints as original prime codes. The use of SPR-codes can reduce both cost and power loss of optical encoders/decoders. Tunable all-optical SPR-code encoders are also designed, which are based on rapidly tunable optical delay lines. It is shown that using this type of encoders not only can further reduce the coding power loss, but also can achieve a very cost-effective fashion.

In this paper, a new encoding/decoding scheme of multiple-valued separable balanced codes is presented. These codes have 2m information digits and m (R - 2) check digits in radices R 4, 2m - 1 information digits and m + 1 check digits in R = 3, where code-length n = Rm. In actual use of code-lengths and radices, it is shown that the presented codes are relatively efficient in comparison with multiple-valued Berger codes which are known as optimal unordered codes. Meanwhile, the optimality of multiple-valued Berger codes is discussed.

The problem of TM-mode scattering from the finite number of rectangular notches in a parallel plate waveguide is considered. The Fourier-transform is employed to obtain simultaneous equations and the simultaneous equations are solved to obtain an analytic solution in rapidly-convergent series. Numerical computations are performed to investigate the scattering behavior in terms of frequency and notch sizes. The presented theory is applicable to the analysis of scattering from the E-plane stubs in the rectangular waveguide.

In this study, we discuss a discrete-time cellular neural network (DTCNN) and its applications including convergence property and stability. Two theorems about the convergence condition of nonreciprocal non-uniform DTCNNs are described, which cover those of reciprocal one as a special case. Thus, it can be applied to wide classes of image processings, such as associative memories, multiple visual patterns recognition and others. Our DTCNN realized by the software simulation can largely reduce the computational time compared to the continuous-time CNN.

An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.