It has been revealed that ion bombardment energy and ion flux density play an essentially critical role in SiNx deposition process of PECVD in TFT-LCD production. Ion energy and ion flux density bombarding onto substrate surface are known to be extracted from waveform of RF applied to an electrode. Using this method, we investigated film quality of SiNx formed in the conventional parallel plate PECVD equipment. When N2 + H2 or N2 + Ar is employed as a carrier gas in source gas (SiH4 + NH3), we have defined normalized ion flux density as ion flux density divided by deposited SiNx molecule which must be increased to obtain high quality SiNx film while ion energy is suppressed at low level as not giving damages on the film surface. This technique has made it possible to securely form SiNx film (2500 ) featuring dielectric break-down field intensity of 8.5 MV/cm at 250 on a glass substrate with Cr gate interconnects of 1000 having vertical step struc-ture. One of the important factors to improve film quality of SiNx deposited in PECVD is to increase ion flux density while keeping ion bombardment energy low enough to protect growing surface against any damages. Using this technique inverse-staggered TFT-array featuring field effect mobility of 0.96 cm2/Vs has been demonstrated which gate insulator SiNx, non-doped a-Si: H and a-Si: H(n+) were formed continuously at the identical substrate temperature of 250.

In order to establish the advanced and costeffective wet cleaning technology, it is essential to reveal the mechanism of contamination adhesion and removal on Si surfaces in solutions. To reveal the mechanism of noble metal adhesion onto the Si surface in wet processes, the behavior of Cu2+ deposition onto Si surfaces in solutions was investigated. The experimental results reveal the mechanism of electrochemical metallic contamination of noble metals on Si surfaces. Moreover, it was found that, in HF solutions, Si is not directly etched in a form of SiF62- by such an oxidizing agent as Cu2+ but is first turned to oxide and then etched off. For preventing noble metal deposition on Si surfaces, it is necessary not only to keep the noble metals in the solution (i.e. to dissolve noble metals) but also to prevent oxidation/reduction reaction between Si and the noble metal ion. It is found that this oxidation/reduction reaction can be prevented by increasing the redox potential of solutions, injecting surfactants or chelating agents, and making the Si surface covered with oxide. It has been revealed that Cu deposition can be prevented by setting the redox potential of the solution at over 0.75 V vs. NHE. Cu deposition in DHF solutions can be prevented by setting the redox potential at 0.85 V vs. NHE or more. For removing Cu from the Si surface, the same conditions are found to be necessary. Moreover, it is revealed that metallic impurities included in the oxide can be removed only by etching. It is also revealed that chemicals to prevent metal deposition must be used to remove metals such as Cu which easily get redeposited on the bare Si surface. Finally, a new wet cleaning process employing ozonized ultrapure water, NH4OH/H2O2/H2O, and surfactant-injected DHF to replace the conventional RCA cleaning method is proposed.

A new line simulator, SEMALIS has been developed. This simulator can handle complicated lot processings to maintain processing quality and efficient line operations to improve line performance. The current manufacturing line consists of five resource models: lot, process sequence, equipment, lot processing, and line operations. The parameters of these models are defined so as to accurately reflect the state of the line operations. From our simulation results, we confirmed that SEMALIS accurately identifies bottlenecks or starvations where equipment can be added or reduced to optimize equipment utilization through resource planning, and that SEMALIS can also be used to evaluate the long-term effects of line operating methods on the line performance of ASIC manufacturing lines.

The purpose of this paper is to provide a practical tool for performing a shift operation in orthonormal compactly supported wavelet bases. This translation τ of a discrete sequence, where τ is a real number, is suitable for filter bank implementations. The shift operation in this realization is neither related to the analysis filters nor to the synthesis filters of the filter bank. Simulations were done on the Daubechis wavelets with 12 coefficients and on complex valued wavelets. For the latter ones a real input sequence was used and split up into two subsequences in order to gain computational efficiency.

Network functions (NFs) such as network reflection and transmission coefficients are discussed about an interconnected network consisting of a lumped distributed N-port N non-commensurate line junction network (N-port) and a M-port. The derivation of the NFs can be done quite easily regardless of the complexity of the network by considering the flow of the traveling waves and conditions of the interconnected interface of the two multi-ports. The theory of this paper has been examined with respect to interconnected networks consisting of two 3-ports in both the time and frequency domains, and has shown good results consistent with other papers. The network functions described here can be used not only for the analysis of high-speed pulse propagation in digital systems with branches but also for the analysis of microwave distributed line networks such as hybird rings. In that sense, a new analysis method is presented in this paper.

This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.

A new yield prediction model has been developed, which can successfully describe the actual chip fabrication yield. It basically consists of modeling of particles deposited on wafer surface, considering the change in their size and spatial distribution due to the subsequent processing steps and a new concept of virtual line width in pattern layouts. It is confirmed that this yield prediction model serves as an effective navigator for improvement/optimization of fabrication lines such as pointing out the process step/equipments to be modified for yield improvements.

In order to simulate the mechanism of particle growth by film deposition, imaginary-particle formation method has been newly developed. By using this formation method, the particle size, the particle height and the position of particle on a wafer could be controlled very easily. In this study, the imaginary-particles of various size larger than 0.15 micron and various height were formed on a wafer. By using these imaginary-particles, the effects of a deposition method, a film thickness, a particle size and a particle height upon the particle growth were investigated. As deposition methods, low pressure CVD method, plasma CVD method and sputtering method were compared. As a result, in all deposition method, it's clear that the particle growth doesn't depend on the initial size, and is proportional to the film thickness. Their particle growth rates are characterized by the deposition method, and their values are 1.9, 1.1 and 0.64 in low pressure CVD, plasma CVD and sputtering method, respectively. These values can be explained by the step coverage decided by the deposition method. Furthermore, the particle growth on imaginary-particle was compared with that on the real-particle. It is clear that the growth mechanism of the real-particle is closely similar to that of imaginary-particle, and the study by use of the imaginary-particle is very effective to make clear the mechanism of particle growth. Therefore, the particle size which should be controlled before deposition process is necessary to be decided by counting the particle growth shown in this paper.

This letter proposes evolutionary digital filters (EDFs) as new adaptive digital filters. The EDF is an adaptive filter which is controlled by adaptive algorithm based on the evolutionary strategies of living things. It consists of many linear/time-variant inner digital filters which correspond to individuals. The adaptive algorithm of the EDF controls and changes the coefficients of inner filters using the cloning method (the asexual reproduction method) or the mating method (the sexual reproduction method). Thus, the search algorithm of the EDF is a non-gradient and multi-point search algorithm. Numerical examples are given to show the effectiveness and features of the EDF such that they are not susceptible to local minimum in the multiple-peak performance surface.

This letter presents an efficient design method of multiplierless 2-D state-space digital filters (SSDFs) based on a genetic algorithm. The resultant multiplierless 2-D SSDFs, whose coefficients are represented as the sum of two powers-of-two terms, are attractive for high-speed operation and simple implementation. The design problem of multiplierless 2-D SSDFs described by Roesser's local state-space model is formulated subject to the constraint that the resultant filters are stable. To ensure the stability for the resultant 2-D SSDFs, a stability test routine is embedded in th design procedure.

We present a new method to cancel interfering sinusoidal signals. In this method, the Interpolated FFT (IpFFT) algorithm is used to estimate the parameters of the interference signal: frequency, amplitude and phase. The cancellation is then performed in the time domain. In order for the IpFFT to perform reliably, accurate spectral information about the interference signal is needed. Since, the information signal masks the interference signal, it becomes difficult to estimate the parameters of the interference signal. To alleviate this masking effect, two techniques are discussed here. These techniques involve frame update of interference spectral information of the interference signal, and adaptive averaging. Significant improvement over conventional frequency domain filterings is achieved. The price paid is only little, beyond the computation of the FFT. Comparison with the conventional frequency domain filter shows that our system has approximately 5dB better cancellation capability for a single interfering signal.

This paper proposes a tool to analyze complicated phenomena from a simple hysteresis network. The simple hysteresis network is described by a piecewise liner ordinal differential equation and has only two parameters: self feedback and DC team. Then this simple system exhibits various kinds of attractors: stable equilibria, periodic orbits, tori and chaos. In order to perform the numerical analysis, we derive return map and propose a fast calculation algorithm for the return map and its Lyapunov exponents based on the exact solutions. Using this algorithm, we have clarified chaos generation and related bifurcation phenomena. Also, we give theoretical formula that give fundamental bifurcation set.

To realize high-speed computations in a residue number system (RNS), an implementation method for residue arithmetic circuits using signed-digit (SD) number representation is proposed. Integers mp = (2p-1) known as Mersenne numbers are used as moduli, so that modulo mp addition can be performed by an end-around-carry SD adder and the addition time is independent of the word length of operands. Using a binary modulo mp SD adder tree, the modulo mp multiplication can be performed in a time proportional to log2p.

Understanding unknown objects in images is one of the most important fields of the computer vision. We are confronted with the problem of dealing with the ambiguity of the image information about unknown objects in the scene. The purpose of this paper is to propose a new object recognition method based on the fuzzy relation system and the fuzzy integral. In order to deal with the ambiguity of the image information, we apply the fuzzy theory to object recognition subjects. Firstly, we define the degree of similarity based on the fuzzy relation system among input images and object models. In the next, to avoid the uncertainty of relations between the input image and the 2-D aspects of models, we integrate the degree of similarity obtained from several input images by the fuzzy integral. This proposing method makes it possible to recognize the unknown objects correctly under the ambiguity of the image information. And the validity of our method is confirmed by the experiments with six kinds of chairs.

This paper reviews Dynamic Channel Allocation (DCA) in TDMA cellular systems. The emphasis is on distributed DCA, which features decentralized control and adaptability to interference. Performance measures are discussed not only from a theoretical viewpoint but also from a practical viewpoint. Major techniques to enhance the capacity of cellular systems are channel segregation, reuse-partitioning, and transmitter power control. In addition to the performance of conventional cellular systems, differing performance in microcellular systems and multi-layer cellular systems is also discussed.

A new dynamic channel allocation algorithm which is integrated with transmitting power control is proposed. By introducing a new threshold, referred to as TPC threshold (Transmitting Power Control threshold), which is added some margin to the threshold of channel allocation, the subsequent transmitting power control can be performed effectively. This DCA algorithm can achieve a cellular system with both high traffic capacity and high service quality such as interference frequency performance simultaneously. The computer simulation shows that this DCA algorithm improves blocking probability performance 4 times better than that of DECT system at 14 Erlang, while keeping the same interference frequency and forced termination performances.

A novel redundancy method suitable for an ultra-high-speed SRAM with logic gates is proposed. Fuse decoders are used to reduce the number of fuses, thus suppressing the access time degradation. This makes it possible to flip chip bond an SRAM with logic gates, which has a high pin count and operates at a very high frequency. To combine the new redundancy method and an ECL decoder circuit with a BiCMOS inverter, several schemes for disabling a defective cell and enabling a spare one are discussed. A 1-Mb ECL-CMOS SRAM with 120-k logic gates was fabricated using 0.3-µm BiCMOS technology. This SRAM consists of 16 RAM macros, and the RAM macro had an access time of only 0.65 ns. The access time degradation after repair was less than 50 ps.

An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.

Threshold voltage shift in high frequency operation of 0.3µm and 0.35µm gate SOI CMOS is experimentally studied, using supply current measurement of inverter chains as test structures. The threshold voltage shift is obtained from the measurement of the leak currents in DC and high frequency condition. For a large supply voltage the electron-hole generation current becomes dominant, resulting in lowered threshold voltage, while the threshold voltage becomes higher than DC case for a low supply voltage. A reasonable relation of the threshold voltage shift and average electric field in the channel is obtained in this study. This method will be useful as a measure of "substrate current" for floating body SOI CMOS.

ElectroStatic Discharge (ESD) testing of integrated circuits subjects circuit elements to very high currents for short periods of time. A modified Transmission Line Pulse (TLP) measurement system for characterizing transistors and other circuit elements under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure leakage. For the TLP system to yield useful information test structures are needed which vary the important design parameters for the circuit elements. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.