Many ATM switching modules with high performance have been proposed and analyzed. A development of a large scale ATM switching system (e.g., used as a central switch) is the key to realization of the broadband ISDN. However, the dimension of ATM switching ICs is limited by the technological and physical constraints on VLSI. A multistage switching configuration is one of the promising configurations for a large scale ATM switch. In this paper, we treat a 3-stage switching configuration with no internal bufferes; i.e., bufferless switches are employed at the first and second stages, and output buffered switches at the third stage. A short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on performance of the bufferless switch used at the first two stages. Furthermore, we propose a 4-stage switching configuration with traffic distributors added at the first stage. This switch provides more paths between a pair of input and output ports than the 3-stage switching configuration mentioned above. A few schemes to distribute cells are compared. It is shown that the distributor successfully reduces the deterioration of cell loss probability due to bursty traffic by splitting incoming cells into several switching modules.

In this paper, we study three-dimensional motion estimation using optical flow. We construct a weighted quotient-form objective function that provides an unbiased estimator. Using this objective function with a certain projection operator as a weight drastically reduces the computational cost for estimation compared with using the maximum likelihood estimator. To reduce the variance of the estimator, we examine the weight, and we show by theoretical evaluations and simulations that, with an appropriate projection function, and when the noise variance is not too small, this objective function provides an estimator whose variance is smaller than that of the maximum likelihood estimator. The use of this projection is based on the knowledge that the depth function has a positive value (i. e., the object is in front of the camera) and that it is generally smooth.

A regeneration technology of fluorite (CaF2) from spent HF and Buffered HF (BHF) has been investigated. The mechanism of "direct conversion" of granular calcite (CaCO3) into granular fluorite has revealed and several special phenomena are first found to be efficient. An advanced system has been developed. This system regenerates granular fluorite by conversion of granular calcite filled in a column. High purity and low water fluorite is recovered as a substitute for natural fluorspar (CaF2). The fluorine concentration in the processed effluent is minimized to a level of 5 ppm. The separation of the HF processing line and BHF processing line equipped ammonia stripper is an important to system design because ammonia generated from BHF significantly retards the conversion efficiency from CaCO3 to CaF2. The new system reforming the conventional slaked lime processing solves long-pending problem, resulting in a very compact system with a very small amount of product.

An adaptive algorithm for a single sinusoid detection using IIR bandpass filter with parallel block structure has been proposed by Nishimura et al. However, the algorithm has three problems: First, it has several input frequencies being impossible to converge. Secondly, the convergence rate can not be higher than that of the scalar structure. Finally, it has a large amount of computation. In this paper, a new algorithm is proposed to solve these problems. In addition, a new structure is proposed to reduce the amount of computation, in which the adaptive control signal generator is realized by the paralel block structure. Simulation results are given to illustrate the performance of the proposed algorithm.

In order to pave the way to B-ISDN, one of the most important issues for network providers is to identify the most efficient B-ISDN introduction strategy. This paper focuses on the costs of introducing ATM transmission systems into backbone transport networks which must provide highly reliable broad band transmission capability. In this context, the main rival to ATM is Synchronous Transfer Mode (STM); recent Synchronous Digital Hierarchy (SDH) equipment supports the establishment of advanced STM-based high speed transport networks. This paper offers a cost comparison of ATM and STM based backbone transport networks. A digital path network in STM has a hierarchical structure determined by the hierarchical multiplexing scheme employed. The minimum cost STM path network can only be determined by developing a path design method that considers all hierarchical path levels and yields the optimum balance of link cost and node cost. Virtual paths have desirable features such as non-deterministic path bandwidth and non-hierarchical and direct multiplexing capability into high speed optical transmission links. These features make it possible to implement a non-hierarchical VP network with ATM cross connect systems which can handle any bandwidth VP with a universal cell switching function. This paper shows that the non-hierarchical VP routing, which strongly minimizes link cost, can be implemented without significantly increasing node cost. Network design simulations show that the virtual path scheme, possible only in an ATM network, yields the most cost effective path network configuration.

Network functions (NFs) such as network reflection and transmission coefficients are discussed about an interconnected network consisting of a lumped distributed N-port N non-commensurate line junction network (N-port) and a M-port. The derivation of the NFs can be done quite easily regardless of the complexity of the network by considering the flow of the traveling waves and conditions of the interconnected interface of the two multi-ports. The theory of this paper has been examined with respect to interconnected networks consisting of two 3-ports in both the time and frequency domains, and has shown good results consistent with other papers. The network functions described here can be used not only for the analysis of high-speed pulse propagation in digital systems with branches but also for the analysis of microwave distributed line networks such as hybird rings. In that sense, a new analysis method is presented in this paper.

In order to establish the advanced and costeffective wet cleaning technology, it is essential to reveal the mechanism of contamination adhesion and removal on Si surfaces in solutions. To reveal the mechanism of noble metal adhesion onto the Si surface in wet processes, the behavior of Cu2+ deposition onto Si surfaces in solutions was investigated. The experimental results reveal the mechanism of electrochemical metallic contamination of noble metals on Si surfaces. Moreover, it was found that, in HF solutions, Si is not directly etched in a form of SiF62- by such an oxidizing agent as Cu2+ but is first turned to oxide and then etched off. For preventing noble metal deposition on Si surfaces, it is necessary not only to keep the noble metals in the solution (i.e. to dissolve noble metals) but also to prevent oxidation/reduction reaction between Si and the noble metal ion. It is found that this oxidation/reduction reaction can be prevented by increasing the redox potential of solutions, injecting surfactants or chelating agents, and making the Si surface covered with oxide. It has been revealed that Cu deposition can be prevented by setting the redox potential of the solution at over 0.75 V vs. NHE. Cu deposition in DHF solutions can be prevented by setting the redox potential at 0.85 V vs. NHE or more. For removing Cu from the Si surface, the same conditions are found to be necessary. Moreover, it is revealed that metallic impurities included in the oxide can be removed only by etching. It is also revealed that chemicals to prevent metal deposition must be used to remove metals such as Cu which easily get redeposited on the bare Si surface. Finally, a new wet cleaning process employing ozonized ultrapure water, NH4OH/H2O2/H2O, and surfactant-injected DHF to replace the conventional RCA cleaning method is proposed.

High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.

This paper proposes a tool to analyze complicated phenomena from a simple hysteresis network. The simple hysteresis network is described by a piecewise liner ordinal differential equation and has only two parameters: self feedback and DC team. Then this simple system exhibits various kinds of attractors: stable equilibria, periodic orbits, tori and chaos. In order to perform the numerical analysis, we derive return map and propose a fast calculation algorithm for the return map and its Lyapunov exponents based on the exact solutions. Using this algorithm, we have clarified chaos generation and related bifurcation phenomena. Also, we give theoretical formula that give fundamental bifurcation set.

We present a new method to cancel interfering sinusoidal signals. In this method, the Interpolated FFT (IpFFT) algorithm is used to estimate the parameters of the interference signal: frequency, amplitude and phase. The cancellation is then performed in the time domain. In order for the IpFFT to perform reliably, accurate spectral information about the interference signal is needed. Since, the information signal masks the interference signal, it becomes difficult to estimate the parameters of the interference signal. To alleviate this masking effect, two techniques are discussed here. These techniques involve frame update of interference spectral information of the interference signal, and adaptive averaging. Significant improvement over conventional frequency domain filterings is achieved. The price paid is only little, beyond the computation of the FFT. Comparison with the conventional frequency domain filter shows that our system has approximately 5dB better cancellation capability for a single interfering signal.

This letter presents an efficient design method of multiplierless 2-D state-space digital filters (SSDFs) based on a genetic algorithm. The resultant multiplierless 2-D SSDFs, whose coefficients are represented as the sum of two powers-of-two terms, are attractive for high-speed operation and simple implementation. The design problem of multiplierless 2-D SSDFs described by Roesser's local state-space model is formulated subject to the constraint that the resultant filters are stable. To ensure the stability for the resultant 2-D SSDFs, a stability test routine is embedded in th design procedure.

This letter proposes evolutionary digital filters (EDFs) as new adaptive digital filters. The EDF is an adaptive filter which is controlled by adaptive algorithm based on the evolutionary strategies of living things. It consists of many linear/time-variant inner digital filters which correspond to individuals. The adaptive algorithm of the EDF controls and changes the coefficients of inner filters using the cloning method (the asexual reproduction method) or the mating method (the sexual reproduction method). Thus, the search algorithm of the EDF is a non-gradient and multi-point search algorithm. Numerical examples are given to show the effectiveness and features of the EDF such that they are not susceptible to local minimum in the multiple-peak performance surface.

This paper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 10,846-transistor circuit, and succeeded in reducing the transistor count by 10%, and the net count by 9%. Transistor sizing and layout compaction reduced the average transistor size by one tenth, while the same delay was maintained. Total circuit capacitance, which is strongly related to power dissipation, was cut to 36%, even when wiring capacitances were dominant.

We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.

In order to simulate the mechanism of particle growth by film deposition, imaginary-particle formation method has been newly developed. By using this formation method, the particle size, the particle height and the position of particle on a wafer could be controlled very easily. In this study, the imaginary-particles of various size larger than 0.15 micron and various height were formed on a wafer. By using these imaginary-particles, the effects of a deposition method, a film thickness, a particle size and a particle height upon the particle growth were investigated. As deposition methods, low pressure CVD method, plasma CVD method and sputtering method were compared. As a result, in all deposition method, it's clear that the particle growth doesn't depend on the initial size, and is proportional to the film thickness. Their particle growth rates are characterized by the deposition method, and their values are 1.9, 1.1 and 0.64 in low pressure CVD, plasma CVD and sputtering method, respectively. These values can be explained by the step coverage decided by the deposition method. Furthermore, the particle growth on imaginary-particle was compared with that on the real-particle. It is clear that the growth mechanism of the real-particle is closely similar to that of imaginary-particle, and the study by use of the imaginary-particle is very effective to make clear the mechanism of particle growth. Therefore, the particle size which should be controlled before deposition process is necessary to be decided by counting the particle growth shown in this paper.

A new yield prediction model has been developed, which can successfully describe the actual chip fabrication yield. It basically consists of modeling of particles deposited on wafer surface, considering the change in their size and spatial distribution due to the subsequent processing steps and a new concept of virtual line width in pattern layouts. It is confirmed that this yield prediction model serves as an effective navigator for improvement/optimization of fabrication lines such as pointing out the process step/equipments to be modified for yield improvements.

A novel redundancy method suitable for an ultra-high-speed SRAM with logic gates is proposed. Fuse decoders are used to reduce the number of fuses, thus suppressing the access time degradation. This makes it possible to flip chip bond an SRAM with logic gates, which has a high pin count and operates at a very high frequency. To combine the new redundancy method and an ECL decoder circuit with a BiCMOS inverter, several schemes for disabling a defective cell and enabling a spare one are discussed. A 1-Mb ECL-CMOS SRAM with 120-k logic gates was fabricated using 0.3-µm BiCMOS technology. This SRAM consists of 16 RAM macros, and the RAM macro had an access time of only 0.65 ns. The access time degradation after repair was less than 50 ps.

It has been revealed that ion bombardment energy and ion flux density play an essentially critical role in SiNx deposition process of PECVD in TFT-LCD production. Ion energy and ion flux density bombarding onto substrate surface are known to be extracted from waveform of RF applied to an electrode. Using this method, we investigated film quality of SiNx formed in the conventional parallel plate PECVD equipment. When N2 + H2 or N2 + Ar is employed as a carrier gas in source gas (SiH4 + NH3), we have defined normalized ion flux density as ion flux density divided by deposited SiNx molecule which must be increased to obtain high quality SiNx film while ion energy is suppressed at low level as not giving damages on the film surface. This technique has made it possible to securely form SiNx film (2500 ) featuring dielectric break-down field intensity of 8.5 MV/cm at 250 on a glass substrate with Cr gate interconnects of 1000 having vertical step struc-ture. One of the important factors to improve film quality of SiNx deposited in PECVD is to increase ion flux density while keeping ion bombardment energy low enough to protect growing surface against any damages. Using this technique inverse-staggered TFT-array featuring field effect mobility of 0.96 cm2/Vs has been demonstrated which gate insulator SiNx, non-doped a-Si: H and a-Si: H(n+) were formed continuously at the identical substrate temperature of 250.

A new line simulator, SEMALIS has been developed. This simulator can handle complicated lot processings to maintain processing quality and efficient line operations to improve line performance. The current manufacturing line consists of five resource models: lot, process sequence, equipment, lot processing, and line operations. The parameters of these models are defined so as to accurately reflect the state of the line operations. From our simulation results, we confirmed that SEMALIS accurately identifies bottlenecks or starvations where equipment can be added or reduced to optimize equipment utilization through resource planning, and that SEMALIS can also be used to evaluate the long-term effects of line operating methods on the line performance of ASIC manufacturing lines.

The purpose of this paper is to provide a practical tool for performing a shift operation in orthonormal compactly supported wavelet bases. This translation τ of a discrete sequence, where τ is a real number, is suitable for filter bank implementations. The shift operation in this realization is neither related to the analysis filters nor to the synthesis filters of the filter bank. Simulations were done on the Daubechis wavelets with 12 coefficients and on complex valued wavelets. For the latter ones a real input sequence was used and split up into two subsequences in order to gain computational efficiency.