We have studied an in situ edge preparation process and the effect of a substrate rotation during the edge preparation in order to improve the uniformity and electrical characteristics of high-Tc edge-type Josephson junctions. The improved YBa2Cu3Ox/PrBa2Cu3Ox/YBa2Cu3Ox edge junctions showed small 1σ-critical current spreads as low as 10% for 12 junctions. We have confirmed that the spreads do not increase significantly by adding groundplane over the junctions. In this paper, we will describe these processes developed for the fabrication of high-Tc superconducting integrated circuits.

In the commonsense reasoning, priorities among rules are often required to be found out in order to derive the desired conclusion as a theorem of the reasoning. In this paper, first we present the bottom-up and top-down abduction procedures to compute skeptical explanations and secondly show that priorities of circumscription to infer a desired theorem can be abduced as a skeptical explanation in abduction. In our approach, the required priorities can be computed based on the procedure to compute skeptical explanations provided in this paper as well as Wakaki and Satoh's method of compiling circumscription into extended logic programs. The method, for example, enables us to automatically find the adequate priority w. r. t. the Yale Shooting Problem to express a human natural reasoning in the framework of circumscription.

A structure and an iterative decoding algorithm of a turbo trellis-coded modulation system, proposed by Robertson and et al. , are improved. For the encoder, removal of the odd-even constraint of an interleaver is discussed and a structure which removes a serial connection of an interleaver and a deinterleaver is proposed. The latter makes encoding delay nearly half. A decoding algorithm which is a natural extension of the standard decoding algorithm to TCM is proposed. In the proposed algorithm, logarithm of an a posteriori probability ratio is divided into three component values: an a priori value, a channel value and an extrinsic information. The extrinsic information is transferred to the next decoding stage as an a priori value. The proposed algorithm is easier to understand than the Robertson's algorithm in which a combination of the channel value and the extrinsic information is transferred to the next stage. Simulation results show the proposed algorithm realizes equivalent or better performance than the Robertson's algorithm. The removal of the odd-even constraint gives a little better performance than that with odd-even constraint in some conditions. By this improvement, bit error rate of 10-5 is obtained at Eb/N0 0. 4 dB from the Shannon limit for 2 bit/symbol transmission with 8-PSK modulation.

An innovative small planar packaging(SPP)system is described that can be combined with card-on-board(COB)packaging in high-speed asynchronous transfer mode switching systems with throughput of over 40-Gb/s. The SPP system provides high I/O pin count density and high packaging density, combining the advantages of both planar packaging used in computer systems and COB packaging used in telecommunication systems. Using a newly developed quasi-coaxial zero-insertion-force connector, point-to-point 311 Mb/s of 8-bit parallel signal transmission is achieved in an arbitrary location on the SPP systems shelf. Also about 5400 I/O connections in the region of the planar packaging system are made, thus the SPP system effectively eliminates the I/O pin count limitation. Furthermore, the heat flux management capability of the SPP system is five times higher than of conventional COB packaging because of its air flow control structure. An SPP system can easily enlarge the switch throughput and it will be useful for future high-speed, high-throughput ATM switching systems.

In general, the performance of partial response maximum-likelihood (PRML) system is degraded by nonlinear distortion and high frequency noise in high-density digital magnetic recording. Conventional PRML system for single-track recording improves the performance when high order PRML systems and high rate codes are adopted. But, in general it is difficult to realize LSI circuits for high order PRML system and high rate code. In this paper, a trellis coded class four partial response maximum-likelihood (TC-PR4ML) system for high density two-track digital magnetic recording is proposed. Our two-track recording method can increase the coding rate over 1, which contributes to a decrease in both degradation effects from partial erasure, one of nonlinear distortions, and high frequency noise in high density recording. The error rate performance of the proposed system is obtained by computer simulation taking account of the partial erasure and it is compared with that of a conventional NRZ coded class four partial response maximum-likelihood (NRZ-PR4ML) system. The results show that the proposed system is hardly affected by partial erasure and keeps good performance in high density recording.

An efficient hybrid scheme has been developed for optimizing register allocation applicable to CISC and RISC processors, which is crucial for maximizing their execution speed. Graph-coloring at the function level is combined with a powerful local register assigner. This assigner uses accurate program flows and access patterns of variables, and optimizes a wider local range, called an extended basic-block (EBB), than other optimizing compilers. The EBB is a set of basic-blocks that constitute a tree-shaped control flow, which is suitable for the large nested branches that frequently appear in embedded system-control programs, such as those for telephone call processing. The coloring at the function level involves only the live-ranges of program variables that span EBBs. The interference graph is therefore very small even for large functions, so it can be constructed quickly. Instead of iterative live-range splitting or spilling, the unallocated live-ranges are optimized by the EBB-based register assigner, so neither load/store insertion nor code motion is needed. This facilitates generating reliable code and debug symbols. The information provided for the EBB-based assigner facilitates the priority-based heuristics, fine-grained interference checking, and deferred coloring, all of which increase the colorability. Using a thread-support package for CHILL as a sample program, performance measurement showed that local variables are successfully located in registers, and the reduction of static cycles is about 20-30%. Further improvements include using double registers and improving debuggability.

We have studied the effect of Ga and Ca substitution in the PrBa2Cu3Oδ (PBCO) barrier on the parameters of high-temperature-superconductor ramp-edge Josephson junctions. Pr 1-XCa XBa2Cu3Oδ (X=0. 15, 0. 3) had reduced bulk barrier resistivity as small as 10 mΩcm which was close to the metal-insulator transition. Also, PrBa2Cu 3-ZGa ZOδ, written as GaZ-doped PBCO (Z=0. 15, 0. 3, 0. 6), had enhanced resistivity neater than 1 kΩcm at 4. 2 K. The transport mechanisms in these bulk barriers fitted well with the Mott variable hopping model. The critical current density Jc and normalized junction conductance (R nA)-1 decayed exponentially with almost the same decay length, as the barrier thickness increased. The decay length depended on the barrier material, and ranged from 1. 7 nm to 6. 5 nm for Jc, from 1. 9 nm to 7. 2 nm for (Rn A)-1. Because on these experimental results, we conclude that direct tunneling is the dominant transport mechanism for both quasi particles and paired particles in our junctions, while resonant tunneling should be considered as an additional transport mechanism of these two kinds of particles in the junctions with the PBCO-based barriers reported so far. It was also found that Ga doping raised the characteristic voltage Vc while Ca doping reduced it, though the Vc values obtained here were still small compared to the theoretically predicted values. The spacewise metal insulator transition at the interfaces caused by a high density of localized states in the barriers seemed to be responsible for the reduction in Vc. The best Vc value was 0. 32 mV at 77 K and 5. 2 mV at 4. 2 K using a Ga0. 6-PBCO barrier. These Vc values are suitable for electronics applications. Furthermore, superconducting-gap-like structures were observed in the junctions with highly resistive Ga-doped PBCO barriers.

Exception handling is not only useful for increasing program readability, but also provides an effective means to check and locate errors, so it increases productivity in large-scale program development. Some typical and frequent program errors, such as out-of-range indexing, null dereferencing, and narrowing violations, cause exceptions that are otherwise unlikely to be caught. Moreover, the absence of a catcher for exceptions thrown by API procedures also causes uncaught exceptions. This paper discusses how the exception handling mechanism should be supported by the compiler together with the operating system and debugging facilities. This mechanism is implemented in the compiler by inserting inline check code and accompanying propagation code. One drawback to this approach is the runtime overhead imposed by the inline check code, which should therefore be optimized. However, there has been little discussion of appropriate optimization techniques and efficiency in the literature. Therefore, a new solution is proposed that formulates the optimization problem as a common assertion elimination (CAE). Assertions consist of check code and useful branch conditions. The latter are effective to remove redundant check code. The redundancy can be checked and removed precisely with a forward iterative data flow analysis. Even in performance-sensitive applications such as telecommunications software, figures obtained by a CHILL optimizing compiler indicate that CAE optimizes the code well enough to be competitive with check suppressed code.

A new traffic engineering and operation of ATM networks is described, which features adaptive virtual path (VP) bandwidth control and VP network reconfiguration capabilities. We call this operation system resilient self-sizing operation. By making full use of self-sizing network (SSN) capabilities, we can operate an ATM network efficiently and keep high robustness against traffic demand fluctuation and network failures, while reducing operating costs. In a multimedia environment, the multimedia services and unpredictability of traffic demand make network traffic management a very challenging problem. SSNs, which are defined as ATM networks with self-sizing traffic engineering and operation capability are expected to overcome these difficulties. This paper proposes VP network operation methods of self-sizing networks for high flexibility and survivability. The VP network operation is composed of adaptive VP bandwidth control to absorb changes in traffic demand, VP rerouting control to recover from failures, and VP network reconfiguration control to optimize the network. The combination of these controls can achieve good performance in flexibility and survivability.

This paper proposes a media synchronization mechanism for live media streams. The mechanism can also handle stored media streams by changing parameter values. The authors have implemented the mechanism on a lip-synch experimental system. Live video and voice streams input at a source workstation are transferred, and then they are synchronized and output at a destination workstation. This paper also evaluates the system performance such as mean square error of synchronization, average output rate, and average delay.

Distributed web caching reduces retrieval latency of World Wide Web (WWW) objects such as text and graphics. Conventional distributed web caching methods, however, require many query messages among cache servers, which limits their scalability and reliability. To overcome these problems, we propose a query caching method in which each cache server caches not only WWW objects but also a query history. This method of finding cached objects can reduce the number of query messages among cache servers, making it possible to construct a large-scale distributed web cache server. We also propose an algorithm for constructing efficient query relationships among cache servers.

A reconfiguration method for processor array is proposed in this paper. In the method, genetic algorithm (GA) is used for searching effective spare arrangement, which leads to successful reconfiguration. The effectiveness of the method is demonstrated by computer simulations.

This letter presents a new algorithm for improving the Signal to Noise Ratio (SNR) of complex sinusoidal signals contaminated by additive Gaussian noises using sum of Higher-Order Statistics (HOS). We conduct some computer simulations to show that the proposed algorithm can improve the SNR more than 7 dB compared with the conventional coherent integration when the SNR of the input signal is -10 dB.

This article shows that a multivalued logic defined as juxtaposition of Boolean binary logics can use all of inference chain, induction and deduction that are important in realization of intelligent inference systems.

This paper proposes a simple learning algorithm that can realize any boolean function using the three-layer binary neural networks. The algorithm has flexible learning functions. 1) moving "core" for the inputs separations,2) "don't care" settings of the separated inputs. The "don't care" inputs do not affect the successive separations. Performing numerical simulations on some typical examples, we have verified that our algorithm can give less number of hidden layer neurons than those by conventional ones.

In order to improve microprocessor performance, we propose to utilize histories of dynamic instruction sequences. A lot of special purpose memories integrated in a processor chip hold the histories. In this paper, we describe the usefulness of using two special purpose memories: Non-Consecutive basic block Buffer (NCB) and Reference Prediction Table (RPT). The NCB improves instruction fetching efficiency in order to relieve control dependences. The RPT predicts data addresses in order to speculate data dependences. From the simulation study, it has been found that the proposed mechanisms improve processor performance by up to 49. 2%.

Recently, a trellis-based recursive maximum likelihood decoding (RMLD) algorithm has been proposed for decoding binary linear block codes. This RMLD algorithm is computationally more efficient than the Viterbi decoding algorithm. However, the computational complexity of the RMLD algorithm depends on the sectionalization of a code trellis. In general, minimization of the computational complexity results in non-uniform sectionalization of a code trellis. From implementation point of view, uniform sectionalization of a code trellis and regularity among the trellis sections are desirable. In this paper, we apply the RMLD algorithm to a class of codes which are transitive invariant. This class includes Reed-Muller (RM) codes, the extended and permuted BCH (EBCH) codes and their subcodes. For this class of codes, the binary uniform sectionalization of a code trellis results in the following regular structure. At each step of decoding recursion, the metric table construction procedure is applied uniformly to all the sections and the size and structure of each metric table are the same. This simplifies the implementation of the RMLD algorithm. Furthermore, for all RM codes of lengths 64 and 128 and EBCH codes of lengths 64 and 128 with relatively low rate, the computational complexity of the RMLD algorithm based on the binary uniform sectionalization of a code trellis is almost the same as that based on an optimum sectionalization of a code trellis.

Conventional approaches to neural network training do not consider possibility of selecting training samples dynamically during the learning phase. Neural network is simply presented with the complete training set at each iteration of the learning. The learning can then become very costly for large data sets. Huge redundancy of data samples may lead to the ill-conditioned training problem. Ill-conditioning during the training causes rank-deficiencies of error and Jacobean matrices, which results in slower convergence speed, or in the worst case, the failure of the algorithm to progress. Rank-deficiencies of essential matrices can be avoided by an appropriate selection of training exemplars at each iteration of training. This article presents underlying theoretical grounds for dynamic sample selection (DSS), that is mechanism enabling to select a subset of training set at each iteration. Theoretical material is first presented for general objective functions, and then for the objective functions satisfying the Lipschitz continuity condition. Furthermore, implementation specifics of DSS to first order line search techniques are theoretically described.

Though response of neurons is mainly decided by synaptic events, the length of a time window for the neuronal response has still not been clarified. In this paper, we analyse the time window within which a neuron processes synaptic events, on the basis of the Hodgkin-Huxley equations. Our simulation shows that an active membrane property makes neurons' behavior complex, and that a few milliseconds is plausible as the time window. A neuron seems to detect coincidence synaptic events in such a time window.

An elastic-Vt CMOS circuit is proposed which facilitates both high speed and low power consumption at low supply voltages. This circuit permits fine-grain power control on each multiple circuit block composing a chip, and it is not sensitive to design factors as device-parameter deviations or operating-environment variations. It also does not require any such additional fabrication technology as triple-well structure or multi-threshold voltage. The effectiveness of the circuits design was confirmed in applying it to specially fabricated 16-bit adders and 4-kb SRAMs based on 1. 5-V, 0. 35- µm CMOS technology.