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  • Reduced State Space Generation of Concurrent Systems Using Weak Persistency

    kunihiko HIRAISHI  

     
    PAPER

      Vol:
    E77-A No:10
      Page(s):
    1602-1606

    State space explosion is a serious problem in analyzing discrete event systems that allow concurrent occurring of events. A new method is proposed for generating reduced state spaces of systems. This method is an improvement of Valmari's stubborn set method. The generated state space preserves liveness, livelocks, and terminal states of the ordinary state space. Petri nets are used as a model of systems, and a method is shown for generating a reduced state space from a given Petri net.

  • Theory of Chemical Waveguides

    Kazuya HAYATA  Masanori KOSHIBA  

     
    LETTER-Electromagnetic Theory

      Vol:
    E77-C No:10
      Page(s):
    1706-1709

    We predict that chemical waves can propagate as a guided mode in a reaction-diffusion system that consists of two regions with different wave speeds. In comparison with electromagnetic waveguides, unique features of the guided chemical waves can be seen in their dispersion characteristics. Conditions for supporting lowest-loss guided waves are discussed.

  • Effect of SiF4/SiH4/H2 Flow Rates on Film Properties of Low-Temperature Polycrystalline Silicon Films Prepared by Plasma Enhanced Chemical Vapor Deposition

    Mikio MOHRI  Hiroaki KAKINUMA  Taiji TSURUOKA  

     
    PAPER-Semiconductor Materials and Devices

      Vol:
    E77-C No:10
      Page(s):
    1677-1684

    We have studied in detail the effect of gas flow rates on the film properties of low-temperature (300) polycrystalline silicon (poly-Si) films prepared by conventional plasma enhanced chemical vapor deposition (13.56 MHz) with SiF4/SiH4/H2 gases. The effect of SiH4 flow rate on crystallization is shown to be large. A small amount of SiH4 with high SiF4 and H2 flow rates (50[H2]/[SiH4]1200, 20[SiF4]/[SiH4]150, 1[H2]/[SiF4]16) is important to form poly-Si films. The poly-Si films deposited under such optimized conditions had shown preferential 〈110〉-orientation and the crystalline fraction is estimated to be more than 80%. The deposition rates are in the range of 5-30 nm/min. The conductivity is in the range of 10-8-10-6 S/cm. Further, the electrical conduction indicates an activation type, and the activation energy is in the range of 0.5-0.6 eV.

  • Stack Tree Automata and Their Relation to Context-Free Grammars with Memory

    Etsuro MORIYA  

     
    PAPER-Automata, Languages and Theory of Computing

      Vol:
    E77-D No:10
      Page(s):
    1086-1093

    As a generalization of the tree automaton, tree automata with various types of memory are introduced and their relation to context-free grammars with memory is studied. Relations between computation trees of tree automata with memory and derivation trees of context-free grammars with memory are established, and as a consequence, the languages generated by context-free grammars with memory are characterized in terms of the sets of trees recognizable by tree automata with memory. Also various types of traversal of labeled trees recognizable by tree automata with memory are considered.

  • Logic Synthesis and Optimization Algorithm of Multiple-Valued Logic Functions

    Ali Massound HAIDAR  Mititada MORISUE  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E77-D No:10
      Page(s):
    1106-1117

    This paper presents a novel and successful logic synthesis method for optimizing ternary logic functions of any given number of input variables. A new optimization algorithm to synthesize and minimize an arbitrary ternary logic function of n-input variables can always lead this function to optimal or very close to optimal solution, where [n (n1)/2]1 searches are necessary to achieve the optimal solution. Therefore, the complexity number of this algorithm has been greatly reduced from O(3n) into O(n2). The advantages of this synthesis and optimization algorithm are: (1) Very easy logic synthesis method. (2) Algorithm complexity is O(n2). (3) Optimal solution can be obtained in very short time. (4) The method can solve the interconnection problems (interconnection delay) of VLSI and ULSI processors, where very fast and parallel operations can be achieved. A transformation method between operational and polynomial domains of ternary logic functions of n-input variables is also discussed. This transformation method is very effective and simple. Design of the circuits of GF(3) operators, addition and multiplication mod-3, have been proposed, where these circuits are composed of Josephson junction devices. The simulation results of these circuits and examples show the following advantages: very good performances, very low power consumption, and ultra high speed switching operation.

  • The Distances between Unrooted and Cyclically Ordered Trees and Their Computing Methods

    Shaoming LIU  Eiichi TANAKA  Sumio MASUDA  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E77-D No:10
      Page(s):
    1094-1105

    Several distances between trees have been proposed. However, most of the reports on distances have dealt with rooted and ordered trees. This paper proposes two distances between unrooted and cyclically ordered trees (CO-trees) and their computing methods. A CO-tree is a tree embedded in a plane. These distances are defined based on Tai's mapping (TM) and a strongly structure preserving mapping (SSPM) between CO-trees. The time complexities to compute the distances between two CO-trees Ta and Tb are OT (N 2aN 2b) for the distance based on a TM and OT(mambNaNb) for that on an SSPM, respectively, where ma(mb) and Na(Nb) are the largest degree of a vertex and the number of vertices of Ta(Tb), respectively. The space complexities of both methods are Os(NaNb). Those distances can be applied to the clustering of CO-trees.

  • Measuring the Student Knowledge State in Concept Learning: An Approximate Student Model

    Enrique Gonzalez TORRES  Takeshi IIDA  Shigeyoshi WATANABE  

     
    PAPER-Artificial Intelligence and Cognitive Science

      Vol:
    E77-D No:10
      Page(s):
    1170-1178

    Among the problems that face ITS designers, the problem of measuring the student knowledge state after concept learning in order to initially adapt a skill acquisition session according to a student's own necessities is a hard one. Typical approaches are the use of some sort of test to assess the student knowledge and choose an initial set of parameters for a session, or use, regardless the particular necessities of a student, a pre-defined set of initial parameters. We consider the fromer to be disrupting for learning and the latter too simple to deal with the broad possibilities that are faced. It is known that students show different behaviors during concept learning depending on the experience, background and actual understanding (the way a student is understanding a concept) during concept learning. Our approach here is to classify the different behaviors through fuzzy proposition and link them with a student model through fuzzy rules to use in an expert system, and with it, select the most suitable problem-solving strategy for each particular student in order to clear his misunderstandings and facilitate the learning of problem-solving skills. The use of probabilistic reasoning (i.e. Bayesian statistics) instead of fuzzy logic is not suitable for the present situation because of the rigidity and precision of the rules that do not allow a proper manipulation of the vagueness involved in the student behavior. We apply this idea to a circuit analysis ITS where the concept learning session is carried out on a Hypertext environment and the skill acquisition session on an interactive problem-solving environment. By tracing the student use of the Hypertext environment we can know the student behavior and use it as a premise in the fuzzy inference.

  • A Pattern Classifier--Modified AFC, and Handwritten Digit Recognition

    Yitong ZHANG  Hideya TAKAHASHI  Kazuo SHIGETA  Eiji SHIMIZU  

     
    PAPER-Artificial Intelligence and Cognitive Science

      Vol:
    E77-D No:10
      Page(s):
    1179-1185

    We modified the adaptive fuzzy classification algorithm (AFC), which allows fuzzy clusters to grow to meet the demands of a given task during training. Every fuzzy cluster is defined by a reference vector and a fuzzy cluster radius, and it is represented as a shape of hypersphere in pattern space. Any pattern class is identified by overlapping plural hyperspherical fuzzy clusters so that it is possible to approximate complex decision boundaries among pattern classes. The modified AFC was applied to recognize handwritten digits, and performances were shown compared with other neural networks.

  • A New Approach for Protocol Synthesis Based on LOTOS

    Bhed Bahadur BISTA  Zixue CHENG  Atsushi TOGASHI  Norio SHIRATORI  

     
    PAPER

      Vol:
    E77-A No:10
      Page(s):
    1646-1655

    In communication protocols, the behaviour of a protocol entity is related to the behaviour of another protocol entity as they communicate under sets of communication rules (protocols). Thus, it is desirable to concentrate on the design of one protocol entity and generate the corresponding protocol entity automatically. Furthermore, it is desirable that the protocol is formal, precise and unambiguous that is, it is described using FDTs (Formal Description Techniques). In this paper, we propose a protocol synthesis algorithm in which, from a LOTOS specification of a single given entity, LOTOS specification of the corresponding peer entity is generated automatically. Unlike previous works, where FSMs (Finite State Machines) were used to synthesize protocols, we use LOTOS, which is one of FDTs developed by ISO, in our proposed synthesis algorithm. We prove that the generated protocol is logical errors free, collectively represented as deadlock free, if the given entity is in certain forms which are natural in the context of connunication protocols.

  • Eigenvalue Bounds for a Certain Class of Interval Matrices

    Takehiro MORI  Hideki KOKAME  

     
    LETTER-Control and Computing

      Vol:
    E77-A No:10
      Page(s):
    1707-1709

    It is shown that for a class of interval matrices we can estimate the location of eigenvalues in a very simple way. This class is characterized by the property that eigenvalues of any real linear combination of member matrices are all real and thus includes symmetric interval matrices as a subclass. Upper and lower bounds for each eigenvalue of such a class of interval matrices are provided. This enables us to obtain Hurwitz stability conditions and Schur ones for the class of interval matrices and positive definiteness conditions for symmetric interval matrices.

  • A Method to Validate the Correctness of Test Logic Programs Applied in a Protocol Conformance Test System Using Petri Nets

    Hiroto SUZUKI  Kohkichi TSUJI  Tetsuo ARAKI  Osamu TAKAHASHI  Shizuo YOSHITAKE  

     
    PAPER

      Vol:
    E77-A No:10
      Page(s):
    1663-1671

    As to the method of multi-layer testing, up to now, the testing system (called PROVES) which testes effectively each N-layer protocol implement of SUT (System Under Test) using the functions of derail-points located between N-layer and (N+1)-layer protocol implements in a test system has been proposed. The test logic programs, which are embedded in the derail-points of the test system, play an important role to realize the protocol error test sequences in the test system. Namely, they modify, add, or delete the correct protocol commands/responses output from the protocol implement part of the lest system, sends these erroneous commands/responses to SUT and observes the output from SUT. This paper proposes the method of validating the correctness of test logic program using the structural properties of Petri nets without coding the test logic programs, where correctness means that the desired output can be obtained by sending or receiving the commands/responses within a constant time under the initial conditions determined uniquely by the test system and SUT. According to our experiment, it is seen that almost all of the logical errors included in the test logic programs used for the experiment can be detected by this method.

  • An Effective Application of Net-Theory to Communication Protocol Development

    Norio SHIRATORI  Eun-Seok LEE  Ken TERUYA  

     
    INVITED PAPER

      Vol:
    E77-A No:10
      Page(s):
    1588-1593

    This paper presents an effective application of Net-theory for all the stages of the communication protocol development process. Net-theory provides a basic mathematical model and tool for development of communication protocol. The special usability of Net-theory is that 1) visual representation of the system's stadic/dynamic structure, so that users may easily understand the represented contents, 2) formal specifications based on mathematical basis of Net-theory admit automatic verification, implementation and conformance testing. We have seen that Net-theory which has the above usability can provide a systematic and advanced paradigm for effective communication protocol development.

  • Modified Deformable Model for Bijective Topology Preserving Map

    Kiichi URAHAMA  Satoshi KAWAKAMI  

     
    LETTER-Bio-Cybernetics and Neurocomputing

      Vol:
    E77-D No:10
      Page(s):
    1186-1188

    A modified deformable model is presented for constructing bijective topology preserving feature maps. The algorithm can solve the optimization problem in the input space as well as that in the output space. A saturating distance function alternative to the Euclid norm is employed to obtain compact space filling maps.

  • Contact Resistance between Plated Conductors and Current Density Distribution in a Contact Spot

    Isao MINOWA  Mitsunobu NAKAMURA  

     
    PAPER-Simulation and AI-Technology

      Vol:
    E77-C No:10
      Page(s):
    1592-1596

    Plating is applied to protect contact surfaces of contact devices such as switch, relay and connector from contaminations of oxidization and sulfuration etc. Furthermore it is known that the contact resistance can be reduced when there exist plated layers on the contact surfaces which have enough thickness and low resistivity compared with substratum materials. In this paper, contact resistance between plated conductors are calculated using three dimensional finite element method. Similariry, current density distribution in a contact spot with various resistivity of plated layers are shown and relative conductance depends on the contact area fraction with thickness of plated layers are presented.

  • Estimation of 3-D Motion from Optical Flow with Unbiased Objective Function

    Norio TAGAWA  Takashi TORIU  Toshio ENDOH  

     
    PAPER-Image Processing, Computer Graphics and Pattern Recognition

      Vol:
    E77-D No:10
      Page(s):
    1148-1161

    This paper describes a noise resistant algorithm for estimating 3-D rigid motion from optical flow. We first discuss the problem of constructing the objective function to be minimized. If a Gaussian distribution is assumed for the niose, it is well-known that the least-squares minimization becomes the maximum likelihood estimation. However, the use of this objective function makes the minimization procedure more expensive because the program has to go through all the points in the image at each iteration. We therefore introduce an objective function that provides unbiased estimators. Using this function reduces computational costs. Furthermore, since good approximations can be analytically obtained for the function, using them as an initial guess we can apply an iterative minimization method to the function, which is expected to be stable. The effectiveness of this method is demonstrated by computer simulation.

  • Optical Path Cross-Connect Node Architecture with High Modularity for Photonic Transport Networks

    Atsushi WATANABE  Satoru OKAMOTO  Ken-ichi SATO  

     
    PAPER-Optical Communication

      Vol:
    E77-B No:10
      Page(s):
    1220-1229

    Creating a bandwidth abundant B-ISDN requires the further development of path technologies. Optical path cross-connect nodes (OXCs) will be required that offer very high levels of expandability. The present limited traffic demands must be efficiently supported while permitting easy step-wise expansion in capacity. This paper proposes two OXC architectures that offer high modularity with regard to incoming/outgoing links or the number of multiplexed wavelengths in each link. This paper briefly reviews, for optical path realization, the wavelength path (WP) and the virtual wavelength path (VWP) techniques. The proposed OXC architectures provide flexibility and minimum investment to encourage introduction but support incremental network growth and investment to match traffic demand. The architectures make it easy to upgrade a WP network to a VWP network, simply by replacing some optical components. It is also shown that the proposed OXC architectures ensure effective optical signal detection after a long-haul optical fiber transmission because they minimizes signal power losses within the OXC. Therefore, the proposed OXC architecture can be applied to global area networks. The proposed OXC architectures will play a key role in realizing the optical path infrastructure for the future bandwidth abundant B-ISDN.

  • On Desirable Fault-Tolerant Topology for Cluster-Based Network

    Kenji ISHIDA  Tohru KIKUNO  

     
    PAPER

      Vol:
    E77-A No:10
      Page(s):
    1617-1622

    Management of control functions in large computer networks is a very difficult problem. One of the effective way to overcome the difficulty is to introduce hierarchical control structure (network cluster) in the management. When a fault occurred in the cluster, routing information at some nodes in the network must be updated in order to react the fault. However, the number of such nodes can be reduced by introducing ingenious topology into the cluster. This paper presents a fundamental discussion on network topology for a network cluster. First, L-FT is defined to represent a degree of fault-tolerance in a cluster with respect to link failures. Secondly, the minimum link problem M is defined to find the minimum number of links to make the cluster L-FT. The following results are obtained. (1) For a network cluster with the fault-tolerant topology 1-FT, at least 2n-2 links have to exist in the cluster where n is the number of border nodes in the cluster. (2) As far as connectivity of the whole network is held, for multiple L link failures in a L-FT cluster, the update of routing information at each node is localized within only the cluster containing the failed links. (3) Several hierarchical networks with fault-tolerant conditions are presented as case studies for a LAN and a MAN.

  • Synthesis of Protocol Specifications from Service Specifications of Distributed Systems in a Marked Graph Model

    Hirozumi YAMAGUCHI  Kozo OKANO  Teruo HIGASHINO  Kenichi TANIGUCHI  

     
    PAPER

      Vol:
    E77-A No:10
      Page(s):
    1623-1633

    In a distributed system, the protocol entities must exchange some data values and synchronization messages in order to ensure the temporal ordering of the events described in a service specification for the distributed system. It is desirable that a correct protocol specification can be derived automatically from a given service specification. In this paper, we propose an algorithm which synthesizes automatically a correct protocol specification from a service specification described as a Marked Graph with Registers (MGR) model and resources (registers and gates) allocation information. This model has a finite control modeled as a marked graph. Therefore, parallel events can be described. In our method, to minimize the number of the exchanged messages, we use a procedure to calculate an optimum solution for 0-1 integer linear programming problems. The number of the steps which each protocol entity needs to simulate one transition in the service specification is also minimized. Ways to avoiding conflict of registers are also described. Our approach has the following advantages. First, parallel events can be described in a service specification. Secondly, many practical systems can be described in the MGR model. Finally, at the protocol specification level, we can understand what events can be executed in parallel.

  • A Parallel Method for the Prefix Convex Hulls Problem

    Wei CHEN  Koji NAKANO  Toshimitsu MASUZAWA  Nobuki TOKURA  

     
    PAPER-Algorithms, Data Structures and Computational Complexity

      Vol:
    E77-A No:10
      Page(s):
    1675-1683

    Given a sorted set S of n points in the plane, the prefix convex hulls problem of S is to compute the convex hull for every prefix set of S. We present a parallel algorithm for this problem. Our algorithm runs in O(logn) time using n/logn processors in the CREW PRAM computational model. The algorithm is shown to be time and cost optimal. One of the techniques we adopt to achieve these optimal bounds is the use of a new parallel data structure Array-Tree.

  • A preconstrained Compaction Method Applied to Direct Design-Rule Conversion of CMOS Layouts

    Hiroshi MIYASHITA  

     
    PAPER-Computer Aided Design (CAD)

      Vol:
    E77-A No:10
      Page(s):
    1684-1691

    This paper describes a preconstrained compaction method and its application to the direct design-rule conversion of CMOS layouts. This approach can convert already designed physical patterns into compacted layouts that satisfy user-specified design rules. Furthermore, preconstrained compaction can eliminate unnecessarily extended diffusion areas and polysilicon wires which tend to be created with conventional longest path based compactions. Preconstrained compaction can be constructed by combining a longest path algorithm with forward and backward slack processes and a preconstraint generation process. This contrasts with previously proposed approaches based on longest path algorithms followed by iterative improvement processes, which include applications of linear programming. The layout styles in those approaches are usually limited to a model where fixed-shaped rectilinear blocks are moved so as to minimize the total length of rectilinear interconnections among the blocks. However, preconstrained compaction can be applied to reshaping polygonal patterns such as diffusion and channel areas. Thus, this compaction method makes it possible to reuse CMOS leaf and macro cell layouts even if design rules change. The proposed preconstrained compaction approach has been applied to direct design-rule conversion from 0.8-µm to 0.5-µm rules of CMOS layouts containing from several to 10,195 transistors. Experimental results demonstrate that a 10.6% reduction in diffusion areas can be achieved without unnecessary extensions of polysilicon wires with a 39% increase in processing times compared with conventional approaches.

21401-21420hit(22683hit)