This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

Considering the trend towards adopting high efficiency picture coding schemes into digital broadcasting services, we investigate objective picture quality scales for evaluating digitally encoded still and moving pictures. First, the study on the objective picture quality scale for high definition still pictures coded by the JPEG scheme is summarized. This scale is derived from consideration of the following distortion factors; 1) weighted noise by the spatial frequency characteristics and masking effects of human vision, 2) block distortion, and 3) mosquito noise. Next, an objective picture quality scale for motion pictures of standard television coded by the hybrid DCT scheme is studied. In addition to the above distortion factors, the temporal frequency characteristics of vision are also considered. Furthermore, considering that all of these distortions vary over time in motion pictures, methods for determining a single objective picture quality value for this time varying distortion are examined. As a result, generally applicable objective picture quality scale is obtained that correlates extremely well with subjective picture quality scale for both still and motion pictures, irrespective of the contents of the pictures. Having an objective scale facilitates automated picture quality evaluation and control.

In this paper, chaos synchronization in coupled discrete-time dynamical systems is studied. Computer results display the interesting synchronization behaviors in the mutually coupled systems. As possible applications of chaos synchronization, parameter estimations and secure communications are proposed. Furthermore, a modified OGY method is given, which converts a chaotic motion into a periodic motion.

A simple solution for the right-angle H-plane waveguide double bend is obtained in analytic series form. The simultaneous equations are solved to obtain the transmission and reflection coefficients in fast convergent series forms. The numerical computations are performed to show the behaviors of the transmission coefficient versus frequency.

We have developed a Virtual Playground," which allows various activities such as virtual playground and virtual visiting areas for hospitalized children who can not usually go outside. A Virtual Playground system is composed of TV monitors, joysticks, cameras, video transmission devices, and a graphics workstation. In a Virtual Playground environment, children can experience what is impossible or difficult during their stay in a hospital. We have completed a couple of experiments already and discussed its effects.* In our recent work, we also introduced a simple version of the Cave display to the Virtual Playground system.

The Hyper Hospital" is a novel medical care system which will be constructed on an electronic information network. The human interface of the Hyper Hospital based on the modern virtual reality technology is expected to enhance patients' ability to heal by providing computer-supported on-line visual consultations. In order to investigate the effects and features of on-line visual consultations in the Hyper Hospital, we conducted an experiment to clarify the influence of electronic interviews on the talking behavior of interviewees in the context of simulated doctor-patient interactions. Four types of distant-confrontation interviews were made with voluntary subjects and their verbal and non-verbal responses were analyzed from the behavioral point of view. The types of interviews included three types of electronic media-mediated interviews and one of a live face to face interview. There was a tendency in the media-mediated interviews that both the latency and the duration of interviewees' utterances in answering questions increased when they were compared with those of live face to face interviews. These results suggest that the interviewee became more verbose or talkative in the media-mediated interviews than in the live interviews. However, the interviewee's psychological tension was generally augmented in the media-mediated interviews, which was suggested by the delay of the initiation of conversations as compared to the conventional face-to-face interviews. We also discuss the applicability of media-mediated interviews by an electronic doctor which we are studying as a functional unit of our Hyper Hospital, a network based virtual reality space for medical care.

In the modern hospital, the physical or chemical therapeutic procedure is regarded as paramount and psychological or spiritual care is quite frequently put aside. The goal of the Hyper Hospital" is to correct this. The Hyper Hospital is constructed in the computer based electronic network using an alternate reality system, such as the virtual reality system, as the human-machine-human interface. The nodes of the Hyper Hospital belong to a patient and also to a variety of medical care facilities; for example, the out patient office, the nursing care center, the medical examination unit, the operating theater, etc. The Hyper Hospital space consists of various kind of spaces including the alternate reality space owned and exclusively controlled by the patient himself or herself, and even the real space as well. Most of the physical contact, such as the visit to the out patient office by the patient, is actualized by the electronic connection of the patient private space and the public space of the hospital system. Prescription drugs, special care, and even the admission to the ward will be integrated into the distributed electronic network. To realize such a system, we need to solve many problems, such as the research on the network oriented architecture of the alternate reality, the development of human-machine interface particularly fitted to various disabilites, the study of the behavior of normal and diseased people, etc. The concept of the Hyper Hospital we are proposing is believed to be a new paradigm of the next generation of medical care.

This paper presents a new sort of multilayer piezoelectric ceramic transformer for switching regulated power supplies. This piezoelectric transformer operates in the second thickness extensional vibration mode. Its resonant frequency is higher than 1 MHz. First, numerical simulation was implemented using a distributed constant electromechanical equivalent circuit method. It was calculated that this piezoelectric transformer, which has higher than 200 mechanical quality factor Qm, could work with higher than 90% efficiency and in more than 20-W/cm3 high power density. Second, a trially fabricated transformer, which is 15 mm long, 15 mm wide and 2.2 mm thick, was examined. Modified PbTiO3 family ceramics were used for the piezoelectric transformer material, because of the large anisotropy between electromechanical coupling factors kt and kp. Obtained results indicate that the piezoelectric transformer has good resonant characteristics, with little spurious vibration, and exhibits 16-W/cm3 power density with high efficiency at 2 MHz. Moreover, a switching regulated power supply, applying the piezoelectric ceramic transformer, was built and examined.

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that a measure of the 'fractal dimension' has been introduced into a logic diagram in such a way that the clustering of modules is iterated while the fractal dimension among clustered modules is retained in a prescribed range. A part of experimental results is also shown, which demonstrates that our clustering approach raises the placement performance much higher than the conventional clustering methods.

This paper compares three typical system-sharing configurations for FTTH networks that provide narrowband and video distribution services and proposes a remote node locating strategy for each configuration. Two new evaluation factors, required land space and service provisioning effort, are included in the calculation, in addition to facility cost and maintenance effort. By considering these factors together, the total network cost is calculated and the sensitivity to the number of remote nodes is evaluated. Finally, the most economical system-sharing configuration is identified on the basis of the evaluations for two typical service areas in Japan, for both present and future cost environments.

The graph bisection problem is to partition a given graph into two subgraphs with equal size with minimizing the cutsize. This problem is NP-hard, and hence several heuristic algorithms have been proposed. Among them, the Kernighan-Lin algorithm and the Fiduccia-Mattheyses algorithm are well known, and widely used in practical applications. Since those algorithms are iterative improvement algorithms, in which the current solution is iteratively improved by interchanging a pair of two nodes belonging to different subgraphs, or moving one node from one subgraph to the other, those algorithms tend to fall into a local optimum. In this paper, we present a heuristic algorithm based on subgraph migration to avoid falling into a local optimum. In this algorithm, an initial solution is given, and it is improved by moving a subgraph, which is effective to reduce the cutsize. The algorithm repeats this operation until no further improvement can be achieved. Finally, the balance of the bisection is restored by moving nodes to get a final solution. Experimental results show that the proposed algorithm gets better solutions than the Kernighan-Lin and Fiduccia-Mattheyses algorithms.

This paper presents an analysis of the control characteristics of the series resonant converter with a parallel resonant circuit, especially under parallel resonant frequency. Operations of the circuit are classified into several modes. The control characteristics are calculated using the equations derived from equivalent circuits, and are verified by the experiments. From the analysis, the mechanism of a jumping phenomenon in the closed-loop control characteristics is clarified.

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.

In this letter an SR-latch circuit using Hopfield neural networks is introduced. An energy function suited for a neural SR-latch circuit is defined for which the global convergence is guaranteed. We also demonstrate how to compose master-slave (M/S) SR- and JK-flip flops of novel SR-latch circuits, and further an asynchronous binary counter of M/S JK-flip flops. Computer simulations are included to illustrate how each presented circuit operates.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

A new rate-controlled queueing discipline, called virtual rate-based queueing (VRBQ), is proposed for packet-switching nodes in connection-oriented, high-speed, wide-area networks. The VRBQ discipline is based on the virtual rate which has a value between the average and peak transmission rates. By choosing appropriate virtual rates, various requirements can be met regarding the performance and quality of services in integrated-service networks. As the worst-case performance guarantee, we determine the upper bounds of queueing delay when VRBQ is combined with an admission control mechanism, i.e., Dynamic Time Windows or Leaky Bucket. Simulation results demonstrate the fairness policy of VRBQ in comparison with other queueing disciplines, and the performance of sources controlled under different virtual rates.

A queueing model suitable for multimedia packets with Poisson and batch Poisson arrivals is studied. In the queueing model, priority is given to the packets with batch Poisson arrival, and the packets with Poisson arrival, accumulated in a buffer, are routed by utilizing intervals of the packets with priority. The queueing performance of the proposed model is evaluated by the mean system delay. We also consider the effect of batch size and the ratio of the traffic with batch Poisson arrival and the one with Poisson arrival on the mean system delay. It is found that the proposed queueing model is useful to reduce the mean system delay of the packets with Poisson arrival, while maintaining the means system delay of the packets with batch Poisson arrival.

A MOS VCO which has improved linearity of oscillation frequency versus control voltage and has no 1/2 divider is studied. The improved VCO characteristic has been obtained by the use of only two additional transistors, one of which has a role of a load and another of which has a role of a control current source in a differential type delay cell.