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21481-21500hit(22683hit)

  • High Speed DRAMs with Innovative Architectures

    Shigeo OHSHIMA  Tohru FURUYAMA  

     
    INVITED PAPER-DRAM

      Vol:
    E77-C No:8
      Page(s):
    1303-1315

    The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

  • A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme

    Hisashi IWAMOTO  Naoya WATANABE  Akira YAMAZAKI  Seiji SAWADA  Yasumitsu MURAI  Yasuhiro KONISHI  Hiroshi ITOH  Masaki KUMANOYA  

     
    PAPER-DRAM

      Vol:
    E77-C No:8
      Page(s):
    1328-1333

    A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

  • Low-Voltage and Low-Power ULSI Circuit Techniques

    Masakazu AOKI  Kiyoo ITOH  

     
    INVITED PAPER-General Technology

      Vol:
    E77-C No:8
      Page(s):
    1351-1360

    Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

  • A Bipolar-Based 0.5 µm BiCMOS Technology on Bonded SOI for High-Speed LSIs

    Makoto YOSHIDA  Toshiro HIRAMOTO  Tsuyoshi FUJIWARA  Takashi HASHIMOTO  Tetsuya MURAYA  Shigeharu MURATA  Kunihiko WATANABE  Nobuo TAMBA  Takahide IKEDA  

     
    PAPER-General Technology

      Vol:
    E77-C No:8
      Page(s):
    1395-1403

    A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

  • 3-D Object Recognition Using Hopfield-Style Neural Networks

    Tsuyoshi KAWAGUCHI  Tatsuya SETOGUCHI  

     
    PAPER-Bio-Cybernetics and Neurocomputing

      Vol:
    E77-D No:8
      Page(s):
    904-917

    In this paper we propose a new algorithm for recognizing 3-D objects from 2-D images. The algorithm takes the multiple view approach in which each 3-D object is modeled by a collection of 2-D projections from various viewing angles where each 2-D projection is called an object model. To select the candidates for the object model that has the best match with the input image, the proposed algorithm computes the surface matching score between the input image and each object model by using Hopfield nets. In addition, the algorithm gives the final matching error between the input image and each candidate model by the error of the pose-transform matrix proposed by Hong et al. and selects an object model with the smallest matching error as the best matched model. The proposed algorithm can be viewed as a combination of the algorithm of Lin et al. and the algorithm of Hong et al. However, the proposed algorithm is not a simple combination of these algorithms. While the algorithm of Lin et al. computes the surface matching score and the vertex matching score berween the input image and each object model to select the candidates for the best matched model, the proposed algorithm computes only the surface matching score. In addition, to enhance the accuracy of the surface matching score, the proposed algorithm uses two Hopfield nets. The first Hopfield net, which is the same as that used in the algorithm of Lin et al., performs a coarse matching between surfaces of an input image and surfaces of an object model. The second Hopfield net, which is the one newly proposed in this paper, establishes the surface correspondences using the compatibility measures between adjacent surface-pairs of the input image and the object model. the results of the experiments showed that the surface matching score obtained by the Hopfield net proposed in this paper is much more useful for the selectoin of the candidates for the best matched model than both the sruface matching score obtained by the first Hopfield net of Lin et al. and the vertex matching score obtained by the second Hopfield net of Lin et al. and, as the result, the object recognition algorithm of this paper can perform much more reliable object recognition than that obtained by simply combining the algorithm of Lin et al. and the algorithm of Hong et al.

  • High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM

    Toshikazu SUZUKI  Toru IWATA  Hironori AKAMATSU  Akihiro SAWADA  Toshiaki TSUJI  Hiroyuki YAMAUCHI  Takashi TANIGUCHI  Tsutomu FUJITA  

     
    PAPER-DRAM

      Vol:
    E77-C No:8
      Page(s):
    1334-1342

    Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level Vpp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the Vpp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at Vcc3.3 V, and also even at Vcc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

  • Necessary and Sufficient Conditions for Unidirectional Byte Error Locating Codes

    Shuxin JIANG  Eiji FUJIWARA  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1246-1252

    The byte error locating codes specify the byte location in which errors are occurred without indicating the precise location of erroneous bit positions. This type of codes is considered to be useful for fault isolation and reconfiguration in the fault-tolerant computer systems. In this paper, difference between the code function of error-location and that of error-correction/error-detection is clarified. With using the concepts of unidirectional byte distance, unordered byte number and ordered byte number, the necessary and sufficient conditions of the unidirectional byte error locating codes are demonstrated.

  • Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories

    Hiroshi ONODA  Yuichi KUNORI  Kojiro YUZURIHA  Shin-ichi KOBAYASHI  Kiyohiko SAKAKIBARA  Makoto OHI  Atsushi FUKUMOTO  Natsuo AJIKA  Masahiro HATANAKA  Hirokazu MIYOSHI  

     
    PAPER-Non-volatile Memory

      Vol:
    E77-C No:8
      Page(s):
    1279-1286

    A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm2 cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm2 cell size for a 0.5 µm 64 Mbit flash memory, is described.

  • Multilevel RLL (D,K,l) Constrained Sequences

    Oscar Yassuo TAKESHITA  Ryuji KOHNO  Hideki IMAI  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1238-1245

    Multilevel RLL (Runlength Limited) sequences are analyzed. Their noiseless capacity and lower bounds on the channel capacity in the presence of additive white Gaussian noise are given. Moreover, the analytical power spectra formulae for those sequences which generalize the previously derived one for binary sequences are newly derived. We conclude from the analysis of the power spectra that multilevel RLL sequences are attractive from the point of view that they increase information rate while keeping low DC-content and self-clocking capability of binary RLL sequences.

  • Design of Repairable Cellular Arrays on Multiple-Valued Logic

    Naotake KAMIURA  Yutaka HATA  Kazuharu YAMATO  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E77-D No:8
      Page(s):
    877-884

    This paper proposes a repairable and diagnosable k-valued cellular array. We assume a single fault, i.e., either stuck-at-O fault or stuck-at-(k1) fault of switches occurs in the array. By building in a duplicate column iteratively, when a stuck-at-(k1) fault occurs in the array, the fault never influences the output of the array. That is, we can construct a fault-tolerant array for the stuck-at-(k1) fault. While, for the stuck-at-O fault, the diagnosing method is simple and easy because we don't have to diagnose the stuck-at-(k1) fault. Moreover, our array can be repaired easily for the fault. The comparison with other rectangular arrays shows that our array has advantages for the number of cells and the cost of the fault diagnosis.

  • Automatic Seal Imprint Verification System with Imprint Quality Assessment Function and Its Performance Evaluation

    Katsuhiko UEDA  

     
    PAPER-Image Processing, Computer Graphics and Pattern Recognition

      Vol:
    E77-D No:8
      Page(s):
    885-894

    An annoying problem encountered in automatic seal imprint verification is that for seal imprints may have a lot of variations, even if they are all produced from a single seal. This paper proposes a new automatic seal imprint verification system which adds an imprint quality assessment function to our previous system in order to solve this problem, and also examines the verification performance of this system experimentally. This system consists of an imprint quality assessment process and a verification process. In the imprint quality assessment process, an examined imprint is first divided into partial regions. Each partial region is classified into one of three quality classes (good quality region, poor quality region, and background) on the basis of characteristics of its gray level histogram. In the verification process, only good quality partial regions of an examined imprint are verified with registered one. Finally, the examined imprint is classified as one of two types: a genuine and a forgery. However, as a result of quality assessment, if the partial regions classified as poor quality are too many, the examined imprint is classified as ambiguous" without verification processing. A major advantage of this verification system is that this system can verify seal imprints of various qualities efficiently and accurately. Computer experiments with real seal imprints were performed by using this system, previous system (without image quality assessment function) and document examiners of a bank. The results of these experiments show that this system is superior in the verification performance to our previous system, and has a similar verification performance to that of document examiners (i.e., the experimental results show the effectiveness of adding the image quality assessment function to a seal imprint verification system).

  • Ultrafast Single-Shot Water and Fat Separated Imaging with Magnetic Field Inhomogeneities

    Shoichi KANAYAMA  Shigehide KUHARA  Kozo SATOH  

     
    PAPER-Medical Electronics and Medical Information

      Vol:
    E77-D No:8
      Page(s):
    918-924

    Ultrafast MR imaging (e.g., echo-planar imaging) acquires all the data within only several tens of milliseconds. This method, however, is affected by static magnetic field inhomogeneities and chemical shift; therefore, a high degree of field homogeneity and water and fat signal separation are required. However, it is practically impossible to obtain an homogeneous field within a subject even if in vivo shimming has been performed. In this paper, we describe a new ultrafast MR imaging method called Ultrafast Single-shot water and fat Separated Imaging (USSI) and a correction method for field inhomogeneities and chemical shift. The magnetic field distribution whthin the subject is measured before thd scan and used to obtain images without field inhomogeneity distortions. Computer simulation results have shown that USSI and the correction method can obtain water and fat separated images as real and imaginary parts, respectively, of a complex Fourier transform with a single-shot scan. Image quality is maintained in the presence of field inhomogeneities of several ppm similar to those occurring under practical imaging conditions. Limitations of the correction method are also discussed.

  • LiNbO3 Optical Modulator Using a Superconducting Resonant Electrode

    Keiji YOSHIDA  Akihiko NOMURA  Yutaka KANDA  

     
    PAPER-LTS

      Vol:
    E77-C No:8
      Page(s):
    1181-1184

    Microwave characteristics of a LiNbO3 optical modulator using a superconductor (Pb-In-Au) as a resonant electrode has been studied experimentally at low temperatures down to 4.2 K. It is shown that at the resonance frequency of 14.8 GHz the obtained modulation depth takes a maximum value as expected from theory when the electrode becomes superconducting. The present results demonstrate the possible applications of superconducting electrodes to high performance LiNbO3 optical modulators.

  • Efficient Cryptosystems over Elliptic Curves Based on a Product of Form-Free Primes

    Hidenori KUWAKADO  Kenji KOYAMA  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1309-1318

    This paper proposes RSA-type cryptosystems over elliptic curves En(O, b) and En(a, O),where En(a, b): y2 x3+ax+b (mod n),and n is a product of from-free primes p and q. Although RSA cryptosystem is not secure against a low exponent attack, RSA-type cryptosystems over elliptic curves seems secure against a low multiplier attack. There are the KMOV cryptosystem and the Demytko cryptosystem that were previously proposed as RSA-type cryptosystems over elliptic curves. The KMOV cryptosystem uses form-restricted primes as p q 2(mod 3)or p q 3(mod 4), and encrypts/decrypts a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem, which is an extension of the KMOV cryptosystem, uses form-free primes, and encrypts/decrypts a log n-bit message over fixed elliptic curves by operating only a value of x coordinates. Our cryptosystems, which are other extensions fo the KMOV cryptosystem, encrypt/decrypt a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem and our cryptosystems have higher security than the KMOV cryptosystem because from-free primes hide two-bit information about prime factors. The encryption/decryption speed in one of our cryptosystems is about 1.25 times faster than that in the Demytko cryptosystem.

  • Performance Analysis of Multi-Pulse Pulse Position Modulation (MPPM) in Noisy Photon Counting Channel

    Tomoaki OHTSUKI  Iwao SASASE  Shinsaku MORI  

     
    LETTER

      Vol:
    E77-A No:8
      Page(s):
    1381-1386

    We analyze the error probability performance of multi-pulse pulse position modulation (MPPM) in noisy photon counting channel. Moreover we investigate the error perofrmance of convolutional coded MPPM and RS coded MPPM in noisy photon counting channel. We define a distance between symbols as the number of nonoverlapping pulses in one symbol, and by using the distance we analyze the error performance of MPPM in noisy photon counting channel. It is shown that MPPM has better performance than PPM in the error probability performance in noisy photon counting channel. For PPM in noisy photon counting channel, convolutional codes are more effective than RS codes to reduce the average transmitting power. For MPPM in noisy photon counting channel, however, RS codes are shown to be more effective than convolutional codes.

  • Stochastic Signal Processing for Incomplete Observations under the Amplitude Limitations in Indoor and Outdoor Sound Environments Based on Regression Analysis

    Noboru NAKASAKO  Mitsuo OHTA  Hitoshi OGAWA  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1353-1362

    A specific signal in most of actual environmental systems fluctuates complicatedly in a non-Gaussian distribution form, owing to various kinds of factors. The nonlinearity of the system makes it more difficult to evaluate the objective system from the viewpoint of internal physical mechanism. Furthermore, it is very often that the reliable observation value can be obtained only within a definite domain of fluctuating amplitude, because many of measuring equipment have their proper dynamic range and the original random wave form is unreliable at the end of amplitude fluctuation. It becomes very important to establish a new signal processing or an evaluation method applicable to such an actually complicated system even from a functional viewpoint. This paper describes a new trial for the signal processing along the same line of the extended regression analysis based on the Bayes' theorem. This method enables us to estimate the response probability property of a complicated system in an actual situation, when observation values of the output response are saturated due to the dynamic range of measuring equipment. This method utilizes the series expansion form of the Bayes' theorem, which is applicable to the non-Gaussian property of the fluctuations and various kinds of correlation information between the input and output fluctuations. The proposed method is newly derived especially by paying our attention to the statistical information of the input-output data without the saturation operation instead of that on the resultantly saturated observation, differing from the well-known regression analysis and its improvement. Then, the output probability distribution for another kind of input is predicted by using the estimated regression relationship. Finally, the effectiveness of the proposed method is experimentally confirmed too by applying it to the actual data observed for indoor and outdoor sound environments.

  • Analysis of an Open-Ended Waveguide as a Probe for Near Field Antenna Measurements by Using TLM Method

    Yoshiyuki FUJINO  Cheuk-yu Edward TONG  

     
    PAPER-Antennas and Propagation

      Vol:
    E77-B No:8
      Page(s):
    1048-1055

    To increase the accuracy of a near field antenna measurement system, it is necessary to know radiation characteristics of a probe to detect near field data. Open ended waveguide used as a near field probe in our system was analyzed using Transmission Line Matrix (TLM) method which is a time domain electromagnetic solver. Validity of this analysis has been confirmed by comparison with experimental data and existing theoretical approximation. Frequency dependence of a complex reflection coefficient at the waveguide aperture has been derived and is shown to agree with measured values. The radiation pattern of the open ended waveguide with mounting structure is also calculated. Ripples on both the amplitude and phase patterns are correctly predicted by our simulation. This method can be applied to accurately model the effect of probe antennas to enhance the accuracy of near field antenna range.

  • A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs

    Tadahiko SUGIBAYASHI  Isao NARITAKE  Hiroshi TAKADA  Ken INOUE  Ichiro YAMAMOTO  Tatsuya MATANO  Mamoru FUJITA  Yoshiharu AIMOTO  Toshio TAKESHIMA  Satoshi UTSUGI  

     
    PAPER-DRAM

      Vol:
    E77-C No:8
      Page(s):
    1323-1327

    A distributive serial multi-bit parallel test scheme for large capacity DRAMs has been developed. The scheme, distributively and serially, extracts and compares the data from cells on a main word-line. This test scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM, the scheme successfully has achieved a 512-bit parallel test.

  • A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories

    Kohji KANAMORI  Yosiaki S. HISAMUNE  Taishi KUBOTA  Yoshiyuki SUZUKI  Masaru TSUKIJI  Eiji HASEGAWA  Akihiko ISHITANI  Takeshi OKAZAWA  

     
    PAPER-Non-volatile Memory

      Vol:
    E77-C No:8
      Page(s):
    1296-1302

    A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.

  • Distortion-Complexity and Rate-Distortion Function

    Jun MURAMATSU  Fumio KANAYA  

     
    PAPER

      Vol:
    E77-A No:8
      Page(s):
    1224-1229

    We define the complexity and the distortion-complexity of an individual finite length string from a finite set. Assuming that the string is produced by a stationary ergodic source, we prove that the distortion-complexity per source letter and its expectation approximate arbitrarily close the rate-distortion function of this source as the length of the string grows. Furthermore, we apply this property to construct a universal data compression scheme with distortion.

21481-21500hit(22683hit)