This paper describes design considerations for high frequency active BPFs up to 100 MHz. The major design issues for high frequency active filters are the excess phase shift in the integrators and high power consumption of the integrators. Typical bipolar transistor based transconductors such as the Gilbert gain cell and the linearized transconductor with two asymmetric emitter-coupled pairs have been analyzed and compared. It has been clarified that the power consumption of the linearized transconductor can be much smaller than that of the Gilbert gain cell because of its high transconductance to working current ratio while maintaining a signal to noise ratio of the same order. A simple high-speed fully differential linearized transconductor cell is proposed with emitter follower buffers and resistive loads for excess phase compensation. A novel gyrator based transformation for the LC ladder BPF has been introduced. This transformation has resulted in a structure with simple capacitor-coupled active resonators which exactly preserves the original transfer function. A fourth order 10.7 MHz BPF IC was designed using the proposed transconductors. It was fabricated and has demonstrated the usefulness of the proposed approach. In addition, an experimental 100 MHz second order BPF IC with Q=14 has been successfully implemented indicating the potential of the proposed approach.

Surface construction is known as a way to visualize volume data. Although currently used algorithms such as marching cubes have good enough quality for volume visualization, they do not ensure adequate surface topology. These algorithms work well when the surface is rather simple. While when complicated, the surface does not separate the internal and external spaces, that is, there exist some holes on the surface, or exist redundant overlaps or self-intersection. Actually, adequate surface topology is important not only for visualization but for laser stereolithography, which creates real 3D plastic objects. In the present paper, we propose a new method that produces a set of triangular patches from a given volume data. The fact that the set of patches has no holes, no redundancy, no self-intersection, and has orientable closed surface topology is shown.

A coplanar-type TW electrode is analyzed for the use within a Ti:LiNbO3 optical modulator. The quasistatic analysis is developed based on the variational principle and the incremental inductance formula. The anisotropy of the LiNbO3, the effect of the SiO2 buffer layer, the overlaid conductor and the electrode thickness can be taken into consideration easily by using the extended spectral domain approach (ESDA) as the formulation procedure. It is shown numerically that the TW electrodes thickness, t, and the overlay spacing, p, are as dominant as the buffer layer thickness d, i.e., the microwave effective index and the product ΔfL is affected significantly by the electrodes thickness t and the overlay spacing, whereas the product VπL is insensitive. Therefore, the introduction of the overlaid conductor and the use of thicker electrodes can be utilized effectively to achieve higher values of the figure of merit Δf/Vπ.

This paper reviews the application of optical technologies to phased array antennas. The performance of the fibre transmission medium and of sources and detectors is reviewed, leading to simple expressions for transmission loss and noise performance. Both coherent and non-coherent beam forming techniques are considered. Future trends, including the use of optical amplifiers and coherent signal generation, will also be discussed.

This letter discusses a microstrip line with an open-end termination in which the reflected microwaves can be optically controlled by a laser illumination. The frequency characteristics are emphasized rather than the time domain ones. The reflection characteristics have been demonstrated experimentally and theoretically for the frequency range of 24 GHz. In the theoretical treatment both the conductance and the capacitance are considered in the equivalent circuit model of the open end of the strip.

Three custom LSIs for EB60, a direct wafer exposure electron beam system, have been developed using 0.8 µm BiCMOS and SST bipolar technologies. The three LSIs are i) a shot cycle control LSI for controlling each exposure cycle time, ii) a linear matrix computation LSI for coordinate modification of the exposure pattern data, and iii) a position calculation LSI for determining the precise position of the wafer. These LSIs allow the deflection corrector block of the revised EB60 to be realized on a single board. A new adaptive pipeline control technique which optimizes each shot period according to the exposure data is implemented in the shot-cycle control LSI. The position calculation LSI implements a new, highly effective 2-level pipeline exposure technique, the levels refer to major-field-deflection and minor-field-deflection. The linear-matrix computation LSI is designed not only for the EB60 but also for a wide variety of parallel digital processing applications.

An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.

This paper reviews the development of low temperature poly Si TFT, scattering light valves addressed by TFTs and a brighter video projection system using them, with the attensin of their optical aspects. The first includes main feature which are laser induced crystallization of PECVD a-Si in almost entirely solid phase by high speed scanning CW Ar laser beam. The second includes photo-polymerization induced phase separation method for the preparation of liquid crystal polymer composite (LCPC) material and scattering light valve with low driving voltage of 6 Vrms. The last gives a brighter video screen image with high contrast ratio and includes higher light efficiency through LCPC light valves and projection lens unit by about four times than that of conventional LC light valves with polarizers.

Stability property of an optically injection-locked semiconductor laser taking account of gain saturation is discussed. Numerical analysis shows that stable locking region is broadened due to gain saturation. This is because of rapid damping of relaxation oscillation due to gain saturation. It is also found that stable locking region is also broadened with increasing injection current since damping of relaxation oscillation becomes strong with increasing injection current. Numerical calculations of lasing spectrum show that the magnitude of sidepeaks appeared at harmonics of relaxation oscillation frequency under unstable locking condition are suppressed due to gain saturation.

Hot carrier stressing is carried out on ultra-thin-film SOI/pMOSFET's under a front gate operation. Degradations of both front and back gate characteristics are estimated. Effects of trapped electron in the front and the back gate oxide on device characteristics are also estimated. In a triode region, it is found that degradation in front gate characteristics is correlated with that in back gate characteristics, although ΔVth(b) is twenty times as large as ΔVth(f), due to difference between the front gate and the buried oxide thickness. In a pentode region, Δβ/β0 in a forward-mode is larger than that in a reverse-mode. This is because of the non-uniformly distributed hot carrier damage along the channel. Based on the charge-coupling theory, damages in the front gate and buried oxide by hot carrier effects are estimated separately. Flat-band-voltage shift in the back gate due to trapped charges in the buried oxide, is obtained from Vth (f) dependence on back gate bias. For Leff=2.0 µm devices, the flat-band-voltage shift varies in the range of 1.00 to 1.50 V. This indicates that trapped electrons are created in the buried oxide. Trapped electrons in the buried oxide increase gm(f) through the effect equivalent to back gate bias. From gm(f) dependence on back gate bias, it is found that effective channel length is decreased by trapped electrons in the front gate oxide near the drain. Therefore, it is worth noticing that, in hot carrier effects in ultra-thin-film SOI/pMOSFET's, gm is increased not only by the reduction of effective channel length but also by the equivalent back gate bias effect.

The newly developed GaAs-pin/SLM, that is structured with a GaAs-pin diode photodetector and a ferroelectric liquid crystal as the light phase modulator, shows the accumulative thresholding characteristic against the optical energy of the write-in pulse train. We experimentally investigate this characteristic and discuss its applications to optical parallel processings.

This paper describes configuration and operation of a high-frequency link resonant inverter using cycloconverter techniques. In this inverter, a resonant link high-frequency voltage generated in a primary resonant inverter is isolated by a high-frequency transformer, then directly converted into a resonant link low-frequency voltage in a cycloconverter. The switching losses and surge voltage levels can be reduced by making all switches in the primary inverter and the cycloconverter operate at zero voltage. The relationship between characteristic impedance of the resonant circuit and the conversion efficiency, and the distortion factor characteristics of the output voltage waveforms are discussed by comparing of analytical and experimental results.

High frequency and low power 128/129 dual modulus prescaler ICs are developed for mobile communication applications, using 0.5 µm GaAs MESFET technology. Provided with an on-chip voltage regulator, a prescaler IC with an input amplifier operates in a wide frequency range from 200 MHz to 1,500 MHz at input power from -15 dBm to +17 dBm at the temperature of -30 to +120 with supply voltage of 2.7 V, 3.0 V and 5.0 V. At the same time, it demonstrated its low power characteristics consuming 3.68 mA with 3.0 V at +30 in operation, 0.16 mA while powered-off. Another prescaler IC without an input amplifier operates up to 1,650 MHz with Vdd=2.7 V, 3.0 V and 5.0 V at +30, dissipating 2.74 mA/3.0 V.

We developed a 32-bit pseudorandom number generator (RNG) operating at liquid nitrogen temperature based on HEMT ICs. It generates maximum-length-sequence codes whose primitive polynomial is X47+X42+1 with the period of 247-1 clock cycle. We designed and fabricated three kinds of cryogenic HEMT IC for this system: A 1306-gate controller IC, a 3319-gate pseudorandom number generator (RNG) IC, and a buffer IC containing a 4-kb RAM and 514 gates. We used 0.6-µm gate-length Se-doped GaAlAs/GaAs HEMTs. Interconnects were Al for the first layer and Au/Pt/Ti for the second layer with a SiON insulator between them. The HEMT ICs have direct-coupled FET logic (DCFL) gates internally and emitter-coupled logic (ECL) compatible input-putput buffers. The unloaded basic delay of the DCFL gate was 17 ps/gate with a power consumption of 1.4 mW/gate at liquid nitrogen temperature. We used an automatic cryogenic wafer probe we developed and an IC tester for function tests, and used a high-speed performance measuring system we also developed with a bandwidth of more than 20 GHz for high-speed performance tests. Power dissipations were 3.8 W for the controller IC, 4.5 W for the RNG IC, and 3.0 W for the buffer IC. The RNG IC, the largest of the three HEMT ICs, had a maximum operating clock rate of 1.6 GHz at liquid nitrogen temperature. We submerged a specially developed zirconium ceramic printed circuit board carrying the HEMT ICs in a closed-cycle cooling system. The HEMT ICs were flip-chip-packaged on the board with bumps containing indium as the principal component. We confirmed that the RNG system operates at liquid nitrogen temperature and measured a minimum system clock period of 1.49 ns.

The mode partition noise of 1.3µm distributed feedback laser diodes (DFB LD's), which is induced by the externally reflected light, is studied experimentally and numerically. The mode partition noise is evaluated by the k-value. It is observed that the mode parition noise monotonically increases with the DC bias current when the reflected light affects DFB LD's and the DC bias current is above the threshold current. From the dependence of the k-value on the external power reflection coefficient, it is observed that the k-value dramatically increases when the external power reflection coefficient is above a value which differs from LD to LD. This is closely related to the fact that the tolerance to the externally reflected light depends on the threshold gain difference between the main mode and the dominant side mode.

A hybrid integrated optical module composed of a silica-based planar lightwave circuit (PLC), a laser diode with an integrated monitor-photodiode, and a pin-photodiode is fabricated for use in high-performance, compact and cost-effective fiber optic subscriber systems. Its applicability to a wavelength-division-multiplex (WDM) system with a 1.3-µm bi-directional signal and a 1.5-µm one-way signal is demonstrated. The PLC was fabricated by a combination of flame hydrolysis deposition (FHD) and reactive ion etching (RIE), and it simultaneously achieved 1.3-µm/1.5-µm multi/demultiplexing and 1.3-µm Y-branching functions. The optical module exhibited insertion losses of 4.1dB at 1.31µm (including a Y-branch circuit loss of 3dB) and 0.5dB at 1.53µm. An optical output power of more than -4dBm was obtained from the optical module and the crosstalk was sufficiently low at less than -20dB between wavelengths of 1.3µm and 1.5µm. Temperature cycle tests on the optical module showed reliable and stable operation with an optical power fluctuation of less than 0.3dB for 500 cycles.

Analysis of the propagation of circularly symmetric fields is made using the finite-difference beam-propagation method. After testing the accuracy of this method, we analyze the guided-mode transmission of connected fibers whose core radii are different. The propagation behavior of the unguided-mode field generated at the junction is revealed using a transparent boundary condition.

Sandwich-type Josephson junctions with the structure Bi2Sr2Ca1Cu2Ox/Bi2Sr2Cu1Oy/Bi2Sr2Ca1Cu2Oz (BSCCO/BSCO/BSCCO), have been fabricated and their characterstics determined. The BSCO barrier layer, which is characterized by a crystal structure close to that of the BSCCO electrode layer, is a normal conductor at 4.2 K. Superconductor/normal-conductor/superconductor (S/N/S) type current-voltage characteristics are obtained with these junctions. Distinctive Shapiro steps are observed when they are exposed to microwave radiation. An oscillating behavior of each step in their I-V characteristics are confirmed for increased microwave power. The critical current, Ic, is found to be proportional to (1-T/Tc)2 in the neighborhood of Tc. These results coincide with the ones observed with conventional S/N/S junctions.

A 1/2 frequency divider using resonant-tunneling hot electron transistors (RHETs) has been proposed and demonstrated. The circuit make the best use of negative differential conductance, a feature of RHETs, and contains one half transistors than used in conventional circuits. The RHETs were fabricated using self-aligned InGaAs RHETs and WSiN thin-film resistors on a single chip. The RHETs have an i-InGaAlAs/i-InGaAs collector barrier that improves the current gain at low collector-base voltages. Circuit operation was confirmed at 77 K.

In this paper the three dimensional (3-D) effect on CMOS latch-up is modeled using a graphical technique based on the fundamental principle of "charge neutrality or its current continuity equivalent" in the base region of parasitic transistors involved in latch-up. The graphical generation of the complete latch-up I-V characteristic requires as an input the SPICE parameters of the relevant bipolar and MOS transistors, the values of shunt resistances and the reverse current-voltage characteristic of the well-substrate junction. The infiuence of the MOS transistor shunting the parasitic bipolar transistors has received special attention. The nonideal scaling of the parasitic resistances has been observed to be the most crucial parameter determining the 3-D nature of the device. The proposed model is validated with test-structures fabricated in 2 µm bulk CMOS technology at and above room temperature. SAFE space map is constructed with width W as a parameter.