This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

We fabricated junctions with a porphyrin polyimide (PORPI) monolayer, and then investigated the electron transport properties of the junctions from the current-voltage (I-V) and d2V/dI2-V measurements. Polyimide LB films without porphyrin were used as tunneling barriers. One large peak was seen at a voltage around 1.9 V, due to the excitation of electron transitions in PORPI molecules, whereas a step structure was not observed in the I-V characteristic.

To investigate the effect of alkyl chain length and adsorption time on the charge-transfer complex formation, ultraviolet-visible absorption and inelastic electron tunneling (IET) spectroscopy measurements were carried out for the tetramethylphenylenediamine (TMPD; donor molecule) adsorbed dodecyl-, pentadecyl- and octadecyl-tetracyanoquinodimethane (TCNQ) Langmuir-Blodgett (LB) films. In the optical absorption spectra, the main peak of LB films shows a red-shift depending on alkyl chain length and adsorption time. Furthermore, the dependence on alkyl chain length and adsorption time are also shown in the IET spectra. These results demonstrate that adsorption LB methods enable to control the adsorption ratio of functional molecules and the CT complex formation.

Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.

Recent developments and case studies regarding VLSI device chip failure analysis are reviewed. The key failure analysis techniques reviewed include EMMS (emission microscopy), OBIC (optical beam induced current), LCM (liquid crystal method), EBP (electron beam probing), and FIB (focused ion beam method). Further, future possibilities in failure analysis, and some promising new tools are introduced.

Following a discussion of various testing methods used in the electron beam (EB) test system, new waveform-based and image-based approaches in the CAD-linked electron beam (EB) test system are proposed. A waveform-based automatic tracing algorithm of the transistor-level performance faults is first discussed. Then, the method to improve the efficiency of an image-based method called dynamic fault imaging (DFI) by fully utilizing the CAD data is described. Third, the VLSI development cost is analyzed by using the fault models that make possible to take into consideration the effect of new testing technologies such as EB testing and focused ion beam (FIB) microfabrication. Finally, the future prospects are discussed.

A method to improve the efficiency of dynamic fault imaging (DFI) by fully utilizing the CAD data in the CAD-linked electron beam test system is proposed. In the method, in order to shorten the long acquisition time of the stroboscopic voltage contrast images over the whole area of the chip during the entire test cycle, only the area and phase (time) required for fault tracing are selected by utilizing the CAD data. Furthermore, image processing techniques are combined with the method to improve the efficiency of the DFI. In particular, the signal averaging technique is used in order to improve the signal-to-noise ratio in the stroboscopic images where all voltage information data on the equipotential electrode recognized by the CAD layout data are averaged. This enables us to reduce the acquisition time of images. Moreover, the experimental system is set up so that the image processing can be performed in parallel with the acquisition of the stroboscopic images. The proposed method is applied to part of a 2k-transistor block of a nonpassivated CMOS LSI where a marginal fault is detected. The result shows that the method is an efficient approach to the fully automatic fault diagnosis in the CAD-linked electron beam test system. The proposed method could improve the efficiency of the conventional DFI by a factor of more than 1000.

Cone and Block methods that sharply reduce logic simulation time in E-beam guided-probe diagnosis are proposed. These methods are based on a primitive-cell-level tracing algorithm, which traces faulty-state cells one by one in the primitive-cell level. By executing logic simulations in these methods so that simulated responses are reported only for the small set of nodes in a tracing path and in the immediate vicinity, simulation CPU time is sharply reduced with state-of-the-art logic simulators such as the Verilog-XL. With the proposed methods, the total CPU time in a diagnostic process can be reduced to 1/700 that of a conventional method. Additionally, the total amount of simulation date also reduces to 1/40 of its original amount. These methods were applied to the guided-probe diagnosis of actual 110k-gate ASIC chips and it was verified that they could be diagnosed in under seven hours per device, which is practical. This technology will greatly contribute to shortening the turnaround time of ASIC development.

Optical and electrical measurements of thin film n-channel SOI-MOSFETs reveal that the exponential tail in photon emission spectra originates from electron-hole recombination. Bremsstrahlung radiation model as a physical mechanism of photon emission was experimentally negated. Negative threshold voltage shift at the initial stage of high field stress is found to be caused by hole trapping in buried oxide. Subsequent turnover characteristics is explained by a competing process between electron trapping in the front gate oxide and hole trapping in the buried oxide. As to the degradation of transconductance, generated surface state as well as trapped holes in the buried oxide which reduce vertical electric field in SOI film are involved in the complicate degradation of transconductance.

The dielectric breakdown characteristics of a thin gate oxide during high-current ion implantation with an electron shower have been investigated by controlling the energy distribution of the electrons. Degradation of the oxide has also been discussed with regard to the total charge injected into the oxide during ion implantation in comparison with that of the TDDB (time dependent dielectric breakdown). Experimental results show that the high-energy and high-density electrons which concentrated in the circumference of the ion beam due to the space charge effect cause the degradation of the thin oxide. It was confirmed that eliminating the high-energy electrons by applying magnetic and electric fields lowers the electron energy at the wafer surface, thereby effectively suppressing the negative charge-up.

An electron beam cell projection system has been developed that can effectively expose the fine, demagnified resultant pattern of repeated and non-repeated patterns such as the 256 Mb DRAM on a semiconductor wafer. Particular attention was given to the beam shaping and deflecting optics, which has two stage deflectors for the cell projection beam selection as well as the beam sizing, and three stage deflectors for objective deflection. The cell mask with a rectangular aperture and multiple figure apertures is fabricated by modified Si wafer processes. A new exposure control data for the cell projection is proposed. This data is fitted for the combination of pattern data for the cell mask projection and pattern data for the variable rectangular shape beam within the divided units of the objective deflection. On this exposure system, selective exposure of the desired pattern becomes possible on the semiconductor wafer while a mounting stage of the wafer is being moved, even if the pattern exposure of the repeated and non-repeated patterns is to be carried out. The total overhead time for selecting a subset of multiple figures and a rectangular aperture of the cell mask is less than 5 seconds/wafer. The estimated throughput of this system is approximately 20 wafers/hour.

An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.

Characterization of silicon devices incorporating the capacitor which uses ferroelectric thin films as capacitor dielectrics is presented. As cases in point, a DRAM cell capacitor and an analog/digital silicon IC using the thin film of barium strontium titanate (Ba1-xSRxTiO3) are examined. Production and characterization of the ferroelectric thin films are also described, focusing on a Metal Organic Deposition technique and liquid source CVD.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

An efficient method which integrates a 2-D energy transport model, impact ionization model, gate current model, a discretized gate-capacitor EPROM model, and a post-processing quasi-transient programming/erase method, was developed for deep-submicron EPROM/Flash device simulation. The predicted results showed on the average better than 90% accuracy, and it took only few minutes CPU time on a SUN/SPARC2 to generate EPROM/Flash Vt shift curves.

New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 109 improvement in device lifetime is achieved.

Directional dry etching of Tantalum is described X-ray lithography absorber patterns. Experiments are carried out using both reactive ion etching in CBrF3-based plasma and electron-cyclotron-resonance ion-stream etching in Cl2-based plasma. Ta absorber patterns with perpendicular sidewalls cannot be obtained by RIE when only CBrF3 gas is used as the etchant. While adding CH4 to CBrF3 effectively improves the undercutting of Ta patterns, it deteriorates etching stability because of the intensive deposition effect of CH4 fractions. By adding an Ar/CH4 mixture gas to CBrF3, it is possible to use RIE to fabricate 0.2-µm Ta absorber patterns with perpendicular sidewalls. ECR ion-stream etching is investigated to obtain high etching selectivity between Ta and SiO2 (etching mask)/SiN (membrane). Adding O2 to the Cl2 etchant improves undercutting without remarkably decreasing etching selectivity. Furthermore, an ECR ion-stream etching method is developed to stably etch Ta absorber patterns finer than 0.2µm. This is successfully applied to X-ray lithography mask fabrication for LSI test devices.

In this paper, the formulation of unified transport model is reviewed along with its implementation in a three-dimensional device simulator. The model features an accurate description of the energy exchange among electrons, holes and lattice, and is therefore suitable for self-consistently simulating thermal effects and non-stationary phenomena, as well as their possible interactions. Despite the model complexity, it is shown that the computational effort required for its solution is reasonably close to more conventional approaches. Application examples are also given, in which both unipolar and bipolar devices are simulated, discussing the relative importance of different phenomena and highlighting the simultaneous occurrence of carrier and lattice heating.

The first demonstration of 88 optical switch matrix with low drive voltage digital optical switch elements is reported. A polarization-independent 88 digital optical switch with drive voltage of 40V at 1.3µm wavelength can be realized by assigning proper lengths for switch elements. The average insertion loss of 10dB and polarization independent switching with average crosstalk of -16dB (limited by the middle stage 22 switch) are achieved.