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[Keyword] electron(432hit)

301-320hit(432hit)

  • Coulomb Blockade Effects in Edge Quantum Wire SOI-MOSFETs

    Akiko OHATA  Akira TORIUMI  

     
    PAPER

      Vol:
    E79-C No:11
      Page(s):
    1586-1589

    The edge of a thin SOI (silicon on insulator) film was used to form a very narrow Si-MOS inversion layer. The ultra-thin SOI film was formed by local oxidation of SIMOX wafer. The thickness of the SOI film is less than 15 nm, i.e., the channel width is narrower than 15 nm. At low tempera-tures, clear and large conductance oscillations were seen in this edge channel MOSFET. These oscillations are explained by Coulomb blockade effects in the narrow channel with several effective potential barriers, since the SOI film is so thin that the channel current is seriously affected by small potential fluctuations in the channel. These results suggest that the channel current in edge quantum wire MOSFET can be cut off even with a small controlled potential change. Furthermore, we fabricated a double-gate edge channel Si-MOSFET. In this device, the channel current can be controlled in two ways. One way is to control the electron number inside the isolated electrodes. The other way is to control the threshold voltage of MOSFET. This device enables us to control the phase of Coulomb oscillation.

  • Room Temperature Operated Single Electron Transistor by STM Nano-Oxidation Process: Fabrication Process and Electrical Properties

    Kazuhiko MATSUMOTO  

     
    INVITED PAPER

      Vol:
    E79-C No:11
      Page(s):
    1509-1514

    New fabrication process for the nano-meter order structure was developed using the STM. The process named "STM nano-oxidation process" could oxidize the titanium metal to form the few tens of nano-meter oxidized titanium line which works as an energy barrier for the electron. The electrical properties of the TiOx line are examined in detail. The single electron transistors with back gate, or side gate, and also those with multi-islands are fabricated using STM nano-oxidation process. The single electron transistor showed the clear Coulomb gap of -160 mV, and the Coulomb oscillation with 400 mV period even at room temperature.

  • The Long-Term Charge Storage Mechanism of Silicon Dioxide Electrets for Microsystems

    Mitsuo ICHIYA  Takuro NAKAMURA  Shuji NAKATA  Jacques LEWINER  

     
    PAPER-Materials

      Vol:
    E79-C No:10
      Page(s):
    1462-1466

    In order to improve the sensitivity of micromachined sensors applied with electrostatic fields and increase their actuated force of electrostatic micromachined actuators, "electrets," which are dielectrics carrying non equilibrium permanent space charges of polarization distribution, are very important. In this paper, positively corona charged silicon dioxide electrets, which are deposited by Plasma Chemical Vapor Deposition (PCVD) and thermally oxidized, are investigated. Physical studies will be described, in which the charge stability is correlated to Thermally Stimulated Current (TSC) measurements and to Electron Spin Resonance (ESR) analysis. Some intrinsic differences have been observed between materials. The electrets with superior long-term charge stability contain 10,000 times as much E' center (Si3 as the ones with inferior long-term charge stability. Finally, some investigations on the long-term charge storage mechanism of the positively charged silicon dioxide electret will be described.

  • Binary Counter with New Interface Circuits in the Extended Phase-Mode Logic Family

    Takeshi ONOMI  Yoshinao MIZUGAKI  TsutomuYAMASHITA  Koji NAKAJIMA  

     
    PAPER-Superconductive digital integrated circuits

      Vol:
    E79-C No:9
      Page(s):
    1200-1205

    A binary counter circuit in the extended phase-mode logic (EPL) family is presented. The EPL family utilizes a single flux quantum as an information bit carrier. Numerical simulations show that a binary counter circuit with a Josephson critical current density of 1 kA/cm2 can operate up to a 30 GHz input signal. The circuit has been fabricated using Nb/AlOx/Nb Josephson junction technology. New interface circuits are employed in the fabricated chip. A low speed test result shows the correct operation of the binary counter.

  • Optimization of the Numbers of Machines and Operators Required for LSI Production

    Kazuyuki SAITO  

     
    PAPER-Integrated Electronics

      Vol:
    E79-C No:8
      Page(s):
    1112-1119

    This paper concerns optimized facility design for VLSI production. The methods proposed are applicable in planning LSI production facilities with a good balance between the number of machines and the number of operators. The sequence in each processing step is analyzed in detail. A new algorithm based on the queueing model is developed for estimating the simultaneous requirements for the two kinds of resources, machines and operators. This estimation system can be applied to complicated fabrication schemes, such as batch processing, continuous processing, and mixed technologies. This methodology yields guidelines for ASIC LSI production system design.

  • A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die

    Yoshiyuki HARAGUCHI  Toshihiko HIROSE  Motomu UKITA  Tomohisa WADA  Masanao EINO  Minoru SAITO  Michihiro YAMADA  Akihiko YASUOKA  

     
    PAPER-Static RAMs

      Vol:
    E79-C No:6
      Page(s):
    743-749

    This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.

  • Predictive Analysis of the Interference on a Dual Polarized Satellite System Due to Cross-Polarization and Differential Rain Attenuation (Gamma Case)

    John D. KANELLOPOULOS  Christos N. VAZOURAS  

     
    PAPER-Antennas and Propagation

      Vol:
    E79-B No:4
      Page(s):
    587-594

    The main propagation effect on interference between adjacent earth-space paths is considered to be the differential rain attenuation. In the present paper, a unified method for the prediction of rain differential attenuation statistics, valid for both single/dual polarization systems, which is based on the two-dimensional gamma distribution, in proposed. The method is particularly oriented for application to earth-space paths located in Japan and other locations with similar climatic conditions. From another point of view, the present work is considered to be the complementary aspect of the present work is considered to be the complementary aspect of the predictive analysis which uses the lognormal assumption. Numerical results are presented referring to communication systems suffering from differential rain attenuation under the hypothesis of using both single and dual polarization.

  • A Large Capacity Photonic ATM Switch Based on Wavelength Division Multiplexing Technology

    Youngbok CHOI  Hideki TODE  Hiromi OKADA  Hiromasa IKEDA  

     
    PAPER-Communication Networks and Services

      Vol:
    E79-B No:4
      Page(s):
    560-568

    Optical switching networks to transport vast amounts of information are important for B-ISDN services. The wavelength division multiplexing (WDM) is emerging as the dominant technology for future optical networks. This paper proposes a large capacity photonic ATM switch architecture using WDM technology. The switch consists of two stages. The first stage is a space switch and the second stage is a wavelength switch. The proposed switch is suitable for WDM optical ATM networks, that is, an input and an output of the switch are wavelength-division-multiplexed. The switch can provide very large ATM cell switching capacity, for instance, 10Tbit/s, with reasonable complexity. The main switch module of the proposed switch has a simple architecture, and reduces the amount of a buffer hardware by introducing the WDM concept.

  • Effects of 50 to 200-keV Electrons by BEASTLI Method on Semiconductor Devices

    Fumio MIZUNO  Satoru YAMADA  Tsunao ONO  

     
    PAPER-Device Issues

      Vol:
    E79-C No:3
      Page(s):
    392-397

    We studied effects of 50-200-keV electrons on semiconductor devices using BEASTLI (backscattered electron assisting LSI inspection) method. When irradiating semiconduc-tor devices with such high-energy electrons, we have to note two phenomena. The first is surface charging and the second is device damage. In our study of surface charging, we found that a net positive charge was formed on the device surface. The positive surface charges do not cause serious influence for observation so that we can inspect wafers without problems. The positive surface charging may be brought about because most incident electrons penetrate the device layer and reach the conducting substrate of the semiconductor device. For the device damage, we studied MOS devices which were sensitive to electron-beam irradiation. By applying a 400- annealing to electron-beam irradiated MOS devices, we could restore the initial characteris-tics of MOS devices. However, in order to recover hot-carrier degradation due to neutral traps, we had to apply a 900- annealing to the electron-beam irradiated MOS devices. Thus, BEASTLI could be successfully used by providing an apporopri-ate annealing to the electron-beam irradiated MOS devices.

  • Control of Fine Particulate and Gaseous Contaminants by UV/Photoelectron Method

    Takafumi SETO  Shin YOKOYAMA  Kikuo OKUYAMA  Masataka HIROSE  Toshiaki FUJII  Hidetomo SUZUKI  

     
    PAPER-Particle/Defect Control and Analysis

      Vol:
    E79-C No:3
      Page(s):
    306-311

    Systems for removing particulates and gaseous contaminants using the UV/photoelectron method under atmospheric and low pressure conditions have been investigated and its availability has been demonstrated. From experimental results, more than 90 % of particulate contaminants are removed by this method under atomospheric and low pressure conditions. This method can be used to design superclean spaces for wafer stockers, and wafer delivering systems in the LSI fabrication process.

  • High-Resolution Wafer Inspection Using the "in-lens SEM"

    Fumio MIZUNO  Satoru YAMADA  Tadashi OHTAKA  Nobuo TSUMAKI  Toshifumi KOIKE  

     
    PAPER-Particle/Defect Control and Analysis

      Vol:
    E79-C No:3
      Page(s):
    317-323

    A new electron-beam wafer inspection system has been developed. The system has a resolution of 5 nm or better, and is applicable to quarter-micron devices such as 256 Mbit DRAMs. The most remarkable feature of this system is that a specimen stage is built in the objective lens and allows a working distance (WD) of 0. "WD=0"minimizes the effect of lens aberrations, and maximizes the resolving power. Innovative designs to achieve WD=0 are as follows: (1)A large objective lens of 730-mm width 730-mm depth 620-mm height that serves as a specimen chamber, has been developed. (2)A hollow specimen stage made of non-magnetic materials has been developed.It allows the lower pole piece and magnetic coile of the objective lens inside it. (3)Acoustic motors made of non-magnetic materials are em-ployed for use in vacuum.

  • Test Structures and a Modified Transmission Line Pulse System for the Study of Electrostatic Discharge

    Robert A. ASHTON  

     
    PAPER-Device and Circuit Characterization

      Vol:
    E79-C No:2
      Page(s):
    158-164

    ElectroStatic Discharge (ESD) testing of integrated circuits subjects circuit elements to very high currents for short periods of time. A modified Transmission Line Pulse (TLP) measurement system for characterizing transistors and other circuit elements under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure leakage. For the TLP system to yield useful information test structures are needed which vary the important design parameters for the circuit elements. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.

  • High-Resolution Determination of Transit Time of Ultrasound in a Thin Layer in Pulse-Echo Method

    Tomohisa KIMURA  Hiroshi KANAI  Noriyoshi CHUBACHI  

     
    PAPER

      Vol:
    E78-A No:12
      Page(s):
    1677-1682

    In this paper we propose a new method for removing the characteristic of the piezoelectric transducer from the received signal in the pulse-echo method so that the time resolution in the determination of transit time of ultrasound in a thin layer is increased. The total characteristic of the pulse-echo system is described by cascade of distributed-constant systems for the ultrasonic transducer, matching layer, and acoustic medium. The input impedance is estimated by the inverse matrix of the cascade system and the voltage signal at the electrical port. From the inverse Fourier transform of input impedance, the transit time in a thin layer object is accurately determined with high time resolution. The principle of the method is confirmed by simulation experiments.

  • A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption

    Katsuhiko UEDA  Toshio SUGIMURA  Toshihiro ISHIKAWA  Minoru OKAMOTO  Mikio SAKAKIHARA  Shinichi MARUI  

     
    PAPER

      Vol:
    E78-C No:12
      Page(s):
    1709-1716

    This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V Vdd.

  • Footprints of Storms on the Sea in the JERS-1 SAR Image

    Toshio IGUCHI  David ATLAS  Ken'ichi OKAMOTO  Akimasa SUMI  

     
    PAPER

      Vol:
    E78-B No:12
      Page(s):
    1580-1584

    SEASAT synthetic aperture radar (SAR) echoes from the sea show beautiful images of storms over the ocean. However, the mechanisms by which such storm images are created have not yet been revealed very well. The core of these images is usually an echo-free hole which is attributed to the damping of the radar-detectable short gravity waves by the intense rain in the storm core. The bright area surrounding the core is believed to be caused by strong winds diverging from the downdraft which is collocated with the intense rain. The outer boundary of the bright area has been found to be associated with the classical gust front. During the Tropical Ocean Global Atmosphere/Coupled Ocean-Atmosphere Response Experiment (TOGA/COARE), continuous observations of rain by shipborne radars were carried out. One image of JERS-1 SAR taken in this period contains storms that were within the observation area of a shipborne radar. The SAR image and the rain-radar image are compared. Even though the signal-to-noise ratio of the SAR image is very low, there is good correspondence between heavy rain areas and some of the dark areas in the SAR image. The boundary of a rain-induced dark area is found to correspond approximately to the radar reflectivity factor (Z-factor) of 35dBZ or 5.5mm/h of rain.

  • Relative Intensity Noise of DFB LD's with Near and Far End Reflections

    Takeshi KAWAI  Adi RAHWANTO  Katsuya KITAJIMA  Masakazu MORI  Toshio GOTO  Akira MIYAUCHI  

     
    PAPER-Opto-Electronics

      Vol:
    E78-C No:12
      Page(s):
    1779-1786

    The relative intensity noise (RIN) spectra of DC driven 1.3 µm distributed feedback laser diodes under the influence of external reflections are measured for various currents and reflection lengths. The effective power reflectivities are 310-4-310-3. The enhanced noise is observed when the relaxation oscillation frequency coincides with the external cavity frequency. It is also observed that the RIN spectra with the near end reflections differ from those with the far end reflections. The degradation of the RIN spectra is analyzed with the rate equations numerically. A new reflection noise model, which includes the carrier density change induced by the reflections, is introduced. The near and far end reflections are characterized well by this model. Furthermore, it is found that the reflection induced noise effect can be described well by the far end reflection noise model even when the reflection length is as short as 1 m.

  • Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System

    Katsuyoshi MIURA  Koji NAKAMAE  hiromu FUJIOKA  

     
    PAPER-Integrated Electronics

      Vol:
    E78-C No:11
      Page(s):
    1607-1617

    An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.

  • Optical Constants of Magnetic Fluids and Their Application to Optical Switches

    Mitsunori SAITO  Makoto TAKAKUWA  Mitsunobu MIYAGI  

     
    PAPER-Opto-Electronics

      Vol:
    E78-C No:10
      Page(s):
    1465-1469

    The complex refractive indices n-jχ of typical magnetic fluids were evaluated for the sake of utilizing them as optical materials. Transmission and reflection spectra were measured in the wavelength range of 0.6-1.6 µm by using monochromators. Magnetic fluids were put into glass cells of 2.5-14-µm thickness for transmission measurement. Due to the absorption by magnetic fluids, the transmittance decreased notably with the increase of the sample thickness. The extinction coefficient χ was evaluated from the dependence of the transmittance on the sample thickness. χ was found to vary between 0.003 and 0.03 depending upon wavelength. The refractive index n was evaluated by fitting theoretical curves to the reflectances that were measured for various incident angles. n was found to vary between 1.6 and 1.7 depending slightly on wavelength. Since a magnetic fluid is a composite of ferrite particles and a solvent, the refractive index can be calculated by using the effective medium theory. The calculated value agreed well with the experimental value. Preliminary experiment of optical switching was also demonstrated by utilizing the mobility of a magnetic fluid.

  • A Design of Switched-Current Auto-Tuning Filter and Its Analysis

    Yoshito OHUCHI  Takahiro INOUE  Hiroaki FUJINO  

     
    PAPER-Analog Signal Processing

      Vol:
    E78-A No:10
      Page(s):
    1350-1354

    In this paper, a new switched-current auto-tuning filter is proposed. Switched-current (SI) is a current-mode analog sampled-data circuit technique. An SI circuit can be realized using only standard digital CMOS technologies, and is capable of realizing high frequency circuits. The proposed filter is composed of SI-OTA (operational transconductance amplifier) integrators. The gain of an SI-OTA integrator can be electronically controlled by the bias current. The proposed filter is a current controlled filter (CCF) and a PLL technique was used as its tuning method. A 2nd-order SI auto-tuning low-pass filter with 100kHz cutoff frequency was designed assuming a 2µm CMOS process. The characteristics of this SI filter and its tuning characteristics were confirmed by SPICE simulations.

  • Growth, Design and Performance of InP-Based Heterostructure Bipolar Transistors

    Kenji KURISHIMA  Hiroki NAKAJIMA  Shoji YAMAHATA  Takashi KOBAYASHI  Yutaka MATSUOKA  

     
    INVITED PAPER

      Vol:
    E78-C No:9
      Page(s):
    1171-1181

    This paper discusses crystal-growth and device-design issues associated with the development of high-performance InP/InGaAs heretostructure bipolar transistors (HBTs). It is shown that a highly Si-doped n+-subcollector in the HBT structure causes anomalous Zn redistribution during metalorganic vapor phase epitaxial (MOVPE) growth. A thermodynamical model of and a useful solution to this big problem are presented. A novel hybrid structure consisting of an abrupt emitter-base heterojunction and a compositionally-graded base is shown to enhance nonequilibrium base transport and thereby increase current gain and cutoff frequency fT. A double-heterostructure bipolar transistor (DHBT) with a step-graded InGaAsP collector can improve collector breakdown behavior without any speed penalty. We also elucidate the effect of emitter size shrinkage on high-frequency performance. Maximum oscillation frequency fmax in excess of 250 GHz is reported.

301-320hit(432hit)