This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

This paper proposes practical escrow cash schemes with particular emphasis on countermeasures against social crimes such as money laundering and extortion. The proposed cash schemes restrict "unconditional" privacy in order to prevent these social crimes while preserving off-line-ness, divisibility and transferability, properties listed in [25] as criteria for ideal cash schemes.

We propose a novel opto-electronic memory device using a single quantum dot (QD) and a logic device using coupled QDs (CQD) which performs (N)AND and (N)OR operations simultaneously. In both devices, occupation/unoccupation by a single electron in a QD is viewed as a bit 1/0 and data input/output (I/O) is performed by irradiation/absorption of photons. The (N)AND/(N)OR operations are performed by the relaxation of the electronic system to the Fock ground state which depends on the number of electrons in the CQD. When the device is constructed of semiconductor nanostructures, the main relaxation process is LA-phonon emission from an electron. Theoretical analysis of the device shows that (i) the error probability in the final state converges with the probability with which the system takes excited states at thermal equilibrium, i. e. , depends only on the dissipation energy and becomes smaller as the dissipation energy becomes larger, and (ii) the speed of operation depends on both the dissipation energy and dissipative interactions and becomes slower as the dissipation energy becomes larger if LA-phonon emission is taken into account. If the QDs are InAs cubes with sides of 10 nm and they are separated by the AlSb barrier with a width of 10 nm, the speed of operation and the error probability are estimated to be about 1 ns and about 0. 2 at 77 K, respectively. The basic idea of the device is applicable to two-dimensional (2D) pattern processing if the devices are arranged in a 2D array.

Gate performance for observing Coulomb oscillations and Coulomb diamonds are compared for two types of gated sub-µm double-barrier heterostructures. The first type of device contains modulation-doped barriers, whereas the second type of device contains a narrower band gap material for the well and no barriers with doped impurities. Both the Coulomb oscillations and Coulomb diamonds are modified irregularly as a function of gate voltage in the first type of device, while in the second type of device they are only systematically modified, reflecting atom-like properties of a quantum dot. This difference is explained in terms of the existence of impurities in the first type of device, which inhomogeneously deform the rotational symmetry of the lateral confining potential as the gate voltage is varied. The absence of impurities is the reason why we observe the atom-like properties only in the second type of device.

We have studied the methods to operate single electron circuits with high reliability at room temperature. By simulation, we have numerically analyzed the error mechanisms of the room-temperature operation of a 2-gate electron pump as a fundamental single electron element circuit. We have found from the results that under the room temperature condition where the ratio of the electrostatic energy to the thermal energy for a transition electron is not so large, the minimum operation error probability is obtained at the specific gate sweep time when the circuit is operated with ramp-waveform control voltages. The analyses indicate that in the shorter sweep time range, the error probability increases because the gate voltage has changed before the significant electron transition occurs, and that in the longer sweep time range, the error probability also increases due to undesired-single-transition events. The optimum sweep time is estimated statically with the relationship between desired- and undesired-single-transition rates as a function of control gate voltages. Using the optimum condition, the operation reliability is expected to be improved by a factor of 100. This estimation method has been also confirmed by the time-dependent Monte-Carlo simulation.

This paper proposes a new associative memory architecture using stochastic behavior in single electron tunneling (SET) devices. This memory stochastically extracts the pattern most similar to the input key pattern from the stored patterns in two matching modes: the voltage-domain matching mode and the time-domain one. In the former matching mode, ordinary associative memory operation can be performed. In the latter matching mode, a purely stochastic search can be performed. Even in this case, by repeating numerous searching trials, the order of similarity can be obtained. We propose a circuit using SET devices based on this architecture and demonstrate its basic operation with a simulation. By feeding the output pattern back to the input, this memory retrieves slightly dissimilar patterns consecutively. This function may be the key to developing highly intelligent information processing systems close to the human brain.

This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.

The basic operation characteristics of an asymmetric turnstile which transfers each electron one by one in one direction is described. A novel single electron counter circuit consisting of the asymmetric turnstiles, a load capacitor and an inverter which counts the number of high inputs is proposed. Monte Carlo circuit simulations reveal that the gate clock time of the counter circuit should be long enough to achieve allowable minimum error rate. The counter circuit implementing asymmetric single electron turnstiles is demonstrated to be applicable to a noise reduction system, a Winner-Take-All circuit and an artificial neuron circuit.

In this paper, we propose a new type of authentication system, one-time zero-knowledge authentication system. Informally speaking, in this authentication system, double usage of the same authentication is prevented. Based on these one-time zero-knowledge authentication systems, we propose a new untraceable electronic cash scheme satisfying both untraceability and unreusablity. This scheme overcomes the problems of the previous scheme proposed by Chaum, Fiat and Naor through its greater efficiency and provable security under reasonable cryptographic assumptions. We also propose a scheme, transferable untraceable electronic cash scheme, satisfying transferability as well as the above two criteria. Moreover, we also propose a new type of electronic cash, untraceable electronic coupon ticket, in which the value of one piece of the electronic cash can be subdivided into many pieces.

New THz radiation devices made of high-Tc superconductors are fabricated and their characteristics are studied in detail. Ultrashort electromagnetic pulses with 0.5 ps width have been radiated into free space from current biased devices made of superconducting YBa2Cu3O7 (YBCO) films by exciting with femtosecond laser pulses. The Fourier spectrum of them extends up to 3 THz. The radiation mechanism is ascribed to the ultrafast supercurrent modulation by the optical pulses. The THz waveform is analyzed using rate equations describing the relaxation of photoexcited quasiparticles. By the improvement of the device structure and the collecting optics, the radiation power can be increased up to 0.5 µW. A new type THz radiation from YBCO films under an external magnetic field without a transport current is also reported.

The high resolution CRT displays used for computer monitor and high performance TV often produce a pattern of bright and dark stripes on the screen called a moire pattern. The elimination of the moire is an important consideration in the CRT design. In this paper, we propose a method for evaluating a moire pattern based on the measurement data of the electron beam distribution. (1) We describe a mathematical expression of the process whereby a moire pattern is produced. By applying the electron beam measurement data into the formulae, precise value of the period and the contrast of a moire are calculated from the actual data of the electron beam profile and the distribution of apertures of the shadow mask. (2) The visibility of the moire is evaluated by plotting the calculation results on the contrastperiod plane, which consists of visible and invisible moire pattern regions based on experimental results of the psychological tests. (3) In addition to the analysis by calculation, the visibility of moire patterns can be visually examined by simulating moire patterns using the same data as above calculation. Since not only fundamental design parameters such as a shadow mask pitch and a scanning line pitch but also details of an electron beam profile such as a distortion or an asymmetry can be examined, a newly developed method contributes the efficiency of the CRT design.

This paper describes a guiding principle for designing functional single-electron tunneling (SET) circuitsthat is a way to elicit the potential functions of a given SET circuit by using as a guiding tool the SET circuit stability diagram. A stability diagram is a map that depicts the stable regions of a SET circuit based on the circuit's variable coordinates. By scrutinizing the diagram, we can infer all the potential functions that can be obtained from a circuit configuration. As an example, we take up a well-known SET-inverter circuit and uncover its latent functions by studying the circuit configuration, based on its stability diagram. We can produce various functions, e.g., step-inverter, Schmidt-trigger, memory cell, literal, and stochastic-neuron functions. The last function makes good use of the inherent stochastic nature of single-electron tunneling, and can be applied to Boltzmann-machine neural network systems.

The performances of an SET required for integration are discussed. Conventional SETs had several problems such as large leakage current, insufficient voltage gain and so on. To overcome these problems, a new SET utilizing Schottky barriers as tunnel junctions is proposed. Its current characteristics and Coulomb-blockade conditions are calculated and the effectiveness for an integrated device is discussed.

Our compact switching converter using a thin-film microtransformer mono-lithically integrated with rectifier diodes represents the first step in developing a monolithic micro-switching converter that can be integrated with semiconductor devices and magnetic components. This converter is a single-ended forward converter with resonant reset and operates successfully at 15 MHz. The maximum output power is 0.5 W.

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.

Two high output-resistance CMOS current mirrors suitable for a low-voltage operation and achieving a high output-swing are presented. They incorporate a modified regulated-cascode, which employs a current-mode amplifier. The main architecture concepts and their detailed schematic examples are discussed. SPICE simulation comparison is shown and the properties of each architecture are pointed out.

A three-terminal quantum device utilizing photon-assisted tunneling in a multilayer structure is proposed and analyzed in terms of its high frequency amplification characteristics. The operation principle of this device includes photonassisted tunneling at the input, formation of a propagating charge wave due to the beat of tunneling electrons and its acceleration, and radiation of electromagnetic waves at the output. Analysis of these operations, discussion of similarities and dissimilarities to classical klystrons, and estimation of the power gain and its frequency dependence are given. A simple example demonstrates that amplification up to the terahertz frequency range is possible using this device.

A Si single electron transistor (SET) was fabricated by converting a one-dimensional Si wire on a SIMOX substrate into a small Si island with a tunneling barrier at each end by means of pattern-dependent oxidation. Since the size of the Si island was as small as around 10 nm owing to this novel technique, the total capacitance of the SET was reduced to a value on the order of 1 aF, which guarantees the conductance oscillation of the SET even at room temperature. Furthermore, a linear relation between the designed wire length and the gate capacitance of SETs was obtained, which clearly indicates that the single island was actually formed in the middle of the one dimensional Si wire. These results were achieved owing to the highly reproducible fabrication process based on pattern dependent oxidation of SIMOX-Si layers. In addition, the fluctuation of the electrical characteristics of the SETs Was studied in relation to the wire size fluctuations. It was found that the fluctuatian is caused predominantly by the roughness of the sidewall surface of the resist pattern.