An InGaP/GaAs composite channel has been proposed in order to improve the electron transport properties of InGaP for high power device applications. The electron mobility and velocity are increased due to the contribution of high mobility GaAs. Although the composite channel FET shows higher transconductance and drain current than those of the InGaP single channel FET, the breakdown voltage is nearly the same. The composite channel FET delivered output power of 0.6 W/mm with power added efficiency of 46.2% under 17 V operation at 1.9 GHz.

Decentralized XML databases are often used in Electronic Commerce (EC) business models such as e-brokers on the Web. To flexibly model such applications, we need a modeling language for EC business processes. To this end, we have adopted a query language approach and have designed a query language, called XBML, for decentralized XML databases used in EC businesses. In this paper, we explain and validate the functionality of XBML by specifying e-broker business models and describe the implementation of the XBML server, focusing on the distributed query processing.

We analyze electron transport of silicon single-electron transistors (Si SETs) with an ultra-small quantum dot using a master-equation model taking into account the discreteness of quantum levels and the finiteness of scattering rates. In the simulated SET characteristics, aperiodic Coulomb blockade oscillations, fine structures and negative differential conductances due to the quantum mechanical effects are superimposed on the usual Coulomb blockade diagram. These features are consistent with the previously measured results. Large peak-to-valley current ratio of negative differential conductances at room temperature is predicted for Si SETs with an ultra-small dot whose size is smaller than 3 nm.

This paper reviews our experimental results for electrical transport properties of nano-scale silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We used very small devices produced using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFETs) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characteristic length to be around 25 nm. We also investigated the energy relaxation mechanism by performing measurements at various applied voltages and temperatures. Furthermore, we clearly observed the tunneling current between the source and drain (source-drain tunneling) in an 8-nm-gate-length EJ-MOSFET. Based on these experimental results, we predict the limitation of MOSFET miniaturization to be around 5 nm in the source-drain tunneling scheme.

Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.

The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.

Personal identity verification has a great variety of applications including access to computer terminals, buildings, credit card verification as well as EC. Algorithms for personal identity verification can be roughly classified into four categories depending on static/dynamic and biometric/physical or knowledge based. Finger prints, iris, retina, DNA, face, blood vessels, for instance, are static and biometric. Algorithms which are biometric and dynamic include lip movements, body movements and on-line signatures. Schemes which use passwords are static and knowledge based, whereas methods using magnetic cards and IC cards are physical. Each scheme naturally has its own advantages and disadvantages. A new algorithm is proposed for pen-input on-line signature verification incorporating pen-position, pen-pressure and pen-inclinations trajectories. A preliminary experiment is performed on a data base consisting of 293 genuine writings and 540 forgery writings, from 8 individuals. Average correct verification rate was 97.6% whereas average forgery refection rate was 98.7%. Since no fine tuning was done, this preliminary result looks very promising.

Smart cards and biometrics can be effectively combined for personal authentication over an open network. The combination is achieved as two-step authentication in which the smart card is authenticated based on a public key infrastructure, and the card holder is authenticated using the template stored in the smart card based on the biometric data. The biometric verification has to be executed in the card for security purposes. This paper describes a fingerprint verification method based on a popular biometric verification technique that can be embedded in a smart card. The prototype system that uses this verification method can verify fingerprints in a few seconds by using the data stored on the smart card.

In a mobile computing environment, the characteristics of wireless communication and host mobility are important considerations in providing an efficient payment service. Currently, most payment systems were not intended for use in a mobile environment, and as such they inherently possess some inefficient properties. In this paper, we propose a new micropayment system (AMPS), designed for use in a mobile computing environment. AMPS reduces the computational load of mobile hosts by directing operations normally performed by the client to the static portion of the network. With AMPS, a client's request for goods goes to a TTP server, called the AMPS server, using only one message. The client can also be disconnected while the AMPS server deals with the merchant, reducing communication costs and power consumption. User privacy is protected by hiding the details of the payment to the AMPS server. The AMPS server can also provide client anonymity to merchants. Another advantage of AMPS is the provision of transaction atomicity by checking goods and money before forwarding to clients or merchants, and preserving all necessary information for any possible future disputes.

This paper proposes a framework for building a customized comparison-shopping system in which the users are allowed to add their own shopping stores dynamically. In this framework, a shopping agent is implemented with a robust inductive learning method that automatically constructs wrappers for semi-structured online stores. During learning, strong biases assumed in many existing systems are weakened so that the real stores with reasonably complex document structures can be handled.

In this paper, we report on design and fabrication of the pipelined digital correlator (PDC) for the opto-electronic discrete correlation processor (OEDCP). The OEDCP consists of optical fan-in and fan-out interconnection systems and several number of PDC's with optical I/O ports. The OEDCP achieves high processing performance with sophisticated combination of optics and electronics. We design and fabricate a prototype of the PDC which is the processing engine of the OEDCP. For the prototype, the pixel number of the input and the output images is 88 and that of the kernel is 33. The designed chip is composed of approximately 10,000 transistors. Operation of the fabricated chip was verified using test vectors.

In this report, a design method of neural networks for limit cycle generator is described. First, the constraint conditions for the synaptic weights, which are given by the linear inequalities, are derived from the dynamics of neural networks. Next, the linear inequalities are solved by the linear programming method. The synaptic weights and other parameters are determined by the above solutions. Furthermore, neuro-based limit cycle generator is designed with analog electronic circuits and simulated by Spice. Finally, we confirm that our design method is efficient and practical for the design of neuro-based limit cycle generator.

As one form of electronic commerce, the scale of online trading in stocks is rapidly growing. Although brokers lie between the customers as trustees in the current market, retrenchment of broker seems inevitable. This paper proposes a protocol that allows trading to proceed with only the market and the customers. We show the required characteristics for this type of trading at first. Next, to fulfil these characteristics, we apply an electronic auction protocol and digital signatures. The result is a trading protocol with security equivalent to that the current trading system.

A fully balanced (FB) transconductor using two multi-input single-ended (SE) CMOS transconductors is proposed, where the transconductors use MOS transitors operating in a triode region for achieving a wide linear input-range. SE circuits are easier to design than differential circuits and inherently reject common-mode (CM) signals. The multi-input structure is used to make a CM feedback loop and to determine an output CM voltage. A high-output-resistance current mirror is used in converting a differential signal to a single-ended signal in order to achieve a high common-mode rejection ratio (CMRR) and a high output-resistance of the transconductor. The FB transconductor achieves a 2-Vpp linear input range at a 2.5-V power supply and consumes 1.74 mA. The output resistance of the FB transconductor is 2 MΩ. It operates at 2 V with a linear input-range of 1.2 Vpp and at 1.6 V with a linear input-range of 0.9 Vpp. A 2.5-V 2.5-MHz FB Gm-C filter using the FB transconductors achieved a CMRR of 45 dB and a passband IIP3 of 32 dBm.

We propose an agent-based grocery shopping system, which automates grocery shopping process. Agents gather grocery information from several store server agents and compare it with user's preferences of groceries and stores. The agents could adapt to user's up-to-date preferences by learning from his/her evaluation of previous shopping results. The proposed agent-based grocery shopping system is composed of three role agents: a user agent, an information management agent, and a store server agent. These role agents cooperate to buy the best groceries of user preference. A role agent is formed by an organization agent. The organization agent is responsible for organizing primitive agents and coordinating message delivery. A primitive agent executes a specific task/function using the accumulated knowledge to achieve user's goal. We have designed four agent communication protocols to facilitate cooperation between the user agent, the information management agent, and the store server agent. In this paper we focus on the protocols which support the user agent. By implementing a prototype of the agent-based grocery shopping system, we have verified that it is instrumental in purchasing the best groceries of user preference from several grocery stores. We have found that, (1) our agent-based grocery shopping system reduces the user's effort to buy groceries; (2) it saves user's time to buy groceries at a store; (3) it covers functional requirements of grocery shopping system from the user's viewpoint; (4) it supports the five stages of consumer buying behavior model.

BaAl2S4:Eu thin-film EL device using a new blue emitting EL phosphor was prepared by the two targets pulse-electron-beam evaporation. The maximum luminance level was 65 cd/m2 under the 50 Hz pulse voltage. The EL spectrum had blue emission with a peak around 470 nm due to the transition for Eu2+ ion. The CIE color coordinates of BaAl2S4:Eu EL device were x = 0.12 and y = 0.10. The performance of blue-emitting BaAl2S4:Eu EL devices is shown to be sufficient for commercial color EL display in color purity and luminance level.

Reducing moire is an important consideration in CRT design. This paper aims to investigate how the visibility of the inverse-phase raster moire, a typical pattern of the raster moire, is influenced by the distribution of the electron beam and the structure of shadow mask apertures. First, a simple model based on the luminance distribution on the CRT screen and characteristics of the human vision was used to calculate the perceived intensity of the inverse-phase raster moire. This calculation was made to examine the effect of model parameters. It showed that the inverse-phase raster moire consists of (1,1)-order moire components. It was also found that the perceived intensity increases with a decrease in electron beam diameter and with an increase in horizontal aperture pitch. In addition, a subjective evaluation test was conducted using an inverse-phase moire pattern reproduced by the image simulation. Test results agreed with the calculated results. Finally, it was revealed that when an electron beam shape having a Gauss distribution was used, most of the raster moire is the inverse-phase raster moire caused by the (1,1)-order component, while the (2,2)-order moire component was very low.

MF (medium frequency) radars (MFR) are powerful tools for understanding the upper atmosphere, by measuring horizontal wind velocity and electron density. This article introduces three MFR systems, two in Japan, Yamagawa (31.20N, 130.62E) and Wakkanai (45.36N, 141.81E) radars, and one at Poker Flat, Alaska (65.1N, 147.5W). Experimental techniques, and their observed results are briefly shown. Horizontal wind velocity was observed by those MFRs, in height ranges of 60-100 km (day) and 80-100 km (night) at Yamagawa and Wakkanai, while the data coverage is unusually low, >54 km (day) and >68 km (night), at Poker Flat. Comparison of MFR winds with temperature observed by a collocated Rayleigh lidar at Poker Flat shows consistency of those two instrument results in terms of atmospheric wave theory, implying validity of MFR data at such low altitudes. Electron density results at Poker Flat agree reasonably with International Reference Ionosphere model values at 74-84 km, and agree well with variation of cosmic noise absorption by the Poker Flat imaging riometer, suggesting valid electron density estimation by MFR at least below 80-85 km.

We present calculations of the linear-response conductance of a SiGe based single-electron transistor (SET). The conductance and the discrete charging of the quantum dot are calculated by free-energy minimization. The free-energy calculation takes the discrete level-spectrum as well as complex many-body interactions into account. The tunneling rates for tunneling through the source and lead barrier are calculated using Bardeen's transfer Hamiltonian formalism. The tunneling matrix elements are calculated for transitions between the zero-dimensional states in the quantum dot and the lowest subband in the one-dimensional constriction. We compare the results for the conductance peaks with those from calculations with a constant tunneling rate where the shape of the peaks is only due to energetic arguments.

Credit-based electronic payment systems are considered to play important roles in future automated payment systems. Like most other types of payment systems, however, credit-based systems proposed so far generally involve computationally expensive cryptographic operations. Such a relatively heavy computational load is preventing credit-based systems from being used in applications which require very fast processing. A typical example is admission-fee payment at the toll gate of an expressway without stopping a vehicle that travels at a high speed. In this article, we propose a very fast credit-based electronic payment protocol for admission-fee payment. More specifically, we propose a payment system between a high-speed vehicle and a toll gate which uses only very simple and fast computations. The proposed system makes use of an optimized Key Pre-distribution System (or KPS) to obtain high resistance against collusion attacks.