We examined the current-voltage (I-V) characteristic of metal/polyimide/rhodamine-dendorimer/polyimide/ metal junctions prepared by the Langmuir-Blodgett (LB) technique. At a temperature of 32.8 K, a step structure was observed in the I-V characteristic, whereas it was not observed for the junctions without rhodamine-dendorimer. The step structure was very similar to that seen in so-called Coulomb staircase. On the basis of the model of Coulomb blockade, the possibility of single electron tunneling via rhodamine-dendrimer (Rh-G2) molecule as a quantum dot was discussed.

Two types of biomimetic chemical sensing systems are reviewed. One is an electronic nose and tongue which can recognize odor or taste from the output pattern of arrayed chemical sensors with different but overlapped specificities. The other is a chemical plume tracing system which has been developed to mimic the moth behavior in tracing the sexual pheromone from a female. We have created an odor/gas tracing robot and a compass, both of which can detect the direction from which an odor/gas is issuing.

This paper presents a universally verifiable Mix-net where the amount of work done by a verifier is independent of the number of mix-servers. Furthermore, the computational task of each mix-server is constant with regard to the number of mix-servers except for some negligible tasks like computing hash function when no disruption occurs. The scheme also provides robustness.

A simple phase compensation technique with improved power supply rejection ratio (PSRR) for CMOS opamps is proposed. This technique is based on feeding back a current proportional to a derivative of the voltage difference between an output and an input, and does not require a common-gate circuit or a noise-free bias for the circuit. The proposed technique requires only two additional transistors, which are connected to the differential pair of transistors in a cascade manner, and the compensation capacitor is connected to the source node of the additional transistor. Experimental results show an improvement of more than 20 dB in the PSRR at high frequencies, comparing the technique with a Miller compensation. This technique also improves the unity gain frequency and the phase margin from 0.9 MHz and 17 to 1.8 MHz and 44 for 200 pF load capacitance, respectively.

10-Gbit/s monolithic receiver OEIC's for 1.55-µm optical transmission systems were fabricated using a stacked layer structure of p-i-n photodiodes and HEMT's grown on InP substrates by single-step MOVPE. A receiver OEIC with a large O/E conversion factor was obtained by adding a three-stage differential amplifier to a conventional feedback amplifier monolithically integrated with a surface-illuminated p-i-n photodiode. The circuit configuration gave a preamplifier a transimpedance of 60 dBΩ. The receiver OEIC achieved error-free operation at 10 Gbit/s without a postamplifier even with the optical input as low as -10.3 dBm because of its large O/E conversion factor of 890 V/W. A two-channel receiver OEIC array for use in a 10-Gbit/s parallel photoreceiver module based on a PLC platform was made by monolithically integrating multimode WGPD's with HEMT preamplifiers. The side-illuminated structure of the WGPD is suitable for integration with other waveguide-type optical devices. The receiver OEIC arrays were fabricated on a 2-inch wafer with achieving excellent uniformity and a yield over 90%: average transimpedance and average 3-dB-down bandwidth were 43.8 dBΩ and 8.0 GHz. The two channels in the receiver OEIC array also showed sensitivities of -16.1 dBm and -15.3 dBm at 10 Gbit/s. The two-channel photoreceiver module was constructed by assembling the OEIC array on a PLC platform. The frequency response of the module was almost the same as that of the OEIC chip and the crosstalk between channels in the module was better than -27 dB in the frequency range below 6 GHz. These results demonstrate the feasibility of using our receiver OEIC's in various types of optical receiver systems.

The present paper modifies the algorithm to estimate harmful event frequencies and examines the definition of modes of operation in IEC 61508. As far as the continuous mode concerns, the calculated results coincide with those obtained based on the standard. However, for the intermediate region of medium demand frequencies and/or medium demand durations, the standard gives much higher harmful event frequencies than the real values. In order to avoid this difficulty, a new definition of modes of operation and a shortcut method for allocation of SILs are presented.

In order to get a perspective to the future of GaN materials, theoretical and experimental knowledge of the optoelectronic activities of dislocations in hexagonal GaN have been reviewed. Although the dislocations in GaN have been thought to be not quite harmful, a growing number of evidences have been accumulated for the intrinsic noxiousness of the dislocations. There are some inconsistencies between experimental data reported by different groups or at different dates, which can be reconciled by a proposed simple model that takes into account the trapping of free excitons. A transmission electron microscopic study revealed that some type of dislocations exhibit the recombination enhanced dislocation glide effect, suggesting the non-radiative recombination activity of the fresh dislocations. Such intrinsic activities of dislocations in GaN, in both electronical and mechanical respects, will possibly cause great difficulties in optoelectronic devices based on this material when the crystal quality becomes improved.

A novel electrical gating circuit is proposed for ultrafast applications in electronics. The circuit employs a two-conductor coupled line, and does not have any active devices such as transistors or diodes. Hence, the ultimate speed of the circuit is limited only by the cutoff frequency of the lines employed. The authors describe the circuit theory and discuss the results of experiments that involved ultrafast measurement using electro-optic sampling techniques. The latter suggests the potential of the circuit to achieve the gatings of at least 80-Gbit/s.

We propose an untraceable electronic money system. Our system uses the partially blind signature based on the discrete logarithm problem, and applies secret key certificates to the payment protocol.

Silicon-based monolithic microwave integrated circuits (MMICs) present an interesting option for low-cost consumer wireless systems. SiGe/Si heterojunction bipolar transistors (HBTs) are a major driving force behind Si-based MMICs, because they offer excellent microwave performance without aggressive lateral scaling. This article reviews opportunities for receiver frontend components (low-noise amplifiers and mixers) using SiGe HBTs.

The relationships between lattice orientation of the electron-beam evaporated MgO layer used as protecting layer for ac plasma displays (ac-PDPs) and the discharge characteristics of color ac-PDPs were investigated by the measurements of ion-induced secondary electron emission. It is proved that values of γi for MgO are large in the order of (220) orientation, (200) orientation, and (111) orientation, that is, γi(220) > γi(200) > γi(111). The values of φ for different lattice orientation are obtained by the measurements of thermionic emission and photo emission. The aging measurements for testing panels with the different lattice orientation of MgO layer revealed that performance of those panels are excellent in the order of (220), (200), and (111). In particular, luminance and luminous efficiency become larger in the order of (220), (200), and (111). It is pointed out that the degree of longevity, sustaining voltage, and memory margin for ac-PDPs with protecting materials as MgO are estimated by the measurements of γi.

For the realization of low-voltage full-color FEDs, requirements for phosphor for the FED are proposed. Especially, the influence of released gases or substances from phosphors on the field emission within the FED was made clear. It was clarified that the analysis of F-N plots of the V-I curve of field emission characteristics was helpful to know the interaction of field emission and phosphors. In the experiment, we first obtained the depth from the phosphor surface of the low voltage electron excitation in case of ZnGa2O4, where the region available for cathodoluminescence at the anode voltage of 400 V is about 63 nm deep from the surface. The characteristic of the 12.4 cm-320(trio)240 pixels low-voltage full-color FED is reported. The luminance of 154 cd/m2 was attained at the anode voltage of 400 V and the duty factor of 1/241. Supported by the high potential of the FED as a flat panel, each problem shall be steadily solved to secure the firm stand as a new full color flat display in new applications.

We developd a method of implementing a multiple-valued Hopfield network on electronic circuits by using single-electron circuit technology. The single-electron circuit shows quantized behavior in its operation because of the discrete tunnel transport of electrons. It can therefore be successfully used for implementing neuron operation of the multiple-valued Hopfield network. The authors developed a single-electron neuron circuit that can produce the staircase transfer function required for the multiple-valued neuron. A method for constructing a multiple-valued Hopfield network by combining the neuron circuits was also developed. A sample network was designed that solves an example of the quadratic integer-programming problem. And a computer simulation demonstrated that the sample network can converge to its optimal state that represents the correct solution to the problem.

An ultra-fast optoelectronic decision circuit using resonant tunneling diodes (RTD's) and a uni-traveling-carrier photodiode (UTC-PD) is proposed. The circuit employs two cascaded RTD's for ultra-fast logic operation and one UTC-PD that offers a direct optical input interface. This novel configuration is suitable for ultra-fast decision operation. Two types of decision circuits are introduced: a positive-logic type and a negative-logic type. Operations of these circuits were simulated using SPICE with precisely investigated RTD and UTC-PD models. In terms of circuit speed, 40-Gbit/s decision and 80-Gbit/s demultiplexing were expected. Furthermore, the superiority of the negative-logic type in terms of the circuit operating margin and the relationship between input peak photocurrent and effective logic swing were clarified by SPICE simulations. In order to confirm the basic functions of the circuits and the accuracy of the simulations, circuits were fabricated by monolithically integrating InP-based RTD's and UTC-PD's. The circuits successfully exhibited 40-Gbit/s decision operation and 80-Gbit/s demultiplexing operation with less than 10-mW power dissipation. The superiority of the negative-logic type circuit for the circuit operation was confirmed, and the relationship between the input peak photocurrent and the effective logic swing was as predicted.

A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.

The current-voltage characteristics of a single electron transistor (SET) in the resonant transport mode are investigated. In the future when SET devices are applied to integrated electronics, the quantum effect will seriously modify their characteristics in ultra-small geometry. The current will be dominated by the resonant transport through narrow energy levels in the dot. The simple case of a two-level system is analyzed and the transport mechanism is clarified. The transport property at low temperatures (higher than the Kondo temperature) in the low tunneling rate limit is discussed, and a current map where current values are classified in the gate bias-drain bias plane is provided. It was shown that the dynamic aspect of electron flow seriously influences the current value.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical 11.55-GHz clock signal from 11.55-Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mW. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and 46.2-Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injection-locked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers.

Tradeoffs between efficiency, power and reliability were analyzed for the GaAs MESFETs with variable recess structures. The MESFET process can be optimized for either best power/efficiency performance or best reliability by varying the width of the first recess. If the first recess width is increased by 0.4 µm, an estimated order of magnitude increase in device lifetime, limited by hot-electron-induced degradation, can be achieved at the expense of 3% in power-added efficiency and 20 mW/mm in output power. The reported hot-electron reliability highlights include maximum sustainable reverse gate current stress of 100 mA/mm and (Stress)(Lifetime) figure of merit of 12.5 Ahr/cm which advances the present state of the art by approximately an order of magnitude. The introduced (Stress)(Lifetime) figure of merit is essential for design-for-reliability of high efficiency power amplifiers.

This paper reports on the use of microelectronic test structures to characterise a novel fabrication technique for thin-film electronic circuit boards. In this technology circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and linewidth for both horizontal and vertical lines are electrically evaluated and these compared with optical and surface profiling measurements.