A quantum interconnection scheme by controlling the Coulomb interaction between ballistic electrons is proposed in which 2DEG (2 dimensional electron gas) plays the role of an interconnection medium. This concept brings up new possibilities for the interconnection approach in various fields such as parallel processing, telecommunications switching, and quantum functional devices. Cross-over interconnection, address collision, and address selection in a quantum information network system were analyzed as the first step. The obtained results have shown that the interconnection probability can be controlled by the velocity and timing of the ballistic electron emission from the emitter electrode. The proposed interconnection scheme is expected to open up a new field of quantum effect integrated circuits in the 21st century.

GaSb/InAs hot electron transistors (HETs) composed of a type-II misaligned quantum well operate at room temperature. The collector current is well described by the thermionic emission from the emitter. In order to get insight of the electron transport in the HET, the base width was varied or the collector barrier was modulated. The emitter's barrier height for the thermionic emission decreases with decreasing base width. This is caused by the increase of the quantum confinement energy in the InAs base with decreasing base width. Among HETs with a GaSb collector, a GaInSb abrupt layer, or a GaInSb graded layer at the collector edge, the latter type has the largest collector current. This indicates that collector grading reduces not only the collector barrier height, but also the quantum mechanical reflection of electrons. Collector-graded HETs with a 5 nm-thick base show a current gain of 8. The sheet resistance of InAs base is one order of magnitude less than bulk InAs without doping. This reduction is partly due to the accumulation of electrons transferred from the GaSb valence band to the InAs conduction band.

The threshold characteristics of mutually coupled SQUIDs (Superconducting Quantum Interference Devices) have been analytically and numerically investigated. The mutually coupled SQUIDs investigated is composed of an rf-SQUID and a dc-SQUID. Here, the rf-SQUID is a flux quantum generator and the dc-SQUID is a flux detector. The linearization method substituting sin-1x by (π/2)x (1x1) is found valid when it is applied to the mutually coupled SQUIDs, because it is possible to obtain the superconducting regions analytically. By computer implementation of linearization method, we found this method is very effective and very quick compared to the ordinary methods. We report the internal flux on an rf-SQUID, the threshold of a dc-SQUID, and that of mutually coupled SQUIDs obtained by Lagrange multiplier formulation and linearization. The features of the threshold characteristics of the mutually coupled SQUIDs with various parameters are also reported. The discontinuous behavior of threshold of the mutually coupled SQUIDs are attractive for digital applications. We suggest three applications of the mutually coupled SQUIDs, that is, a logic gate for high-Tc superconductors (HTSs), a neuron device, and an A/D converter.

In order to investigate the characteristics of the superconducting gap structures of BSCCO oxide superconductor, tunneling spectrum measurements were carried out with several junctions on the bulk single crystal surfaces. Point contact tunneling studies by means of the M/I/S and S/(I)/S junctions have shown the reproducible gap values, 2Δ (//c-axis) of 402 meV, at the cleaved crystal surfaces, and the ratio of 2Δ(//)/kBTc5.50.3 indicates the strong coupling superconductor of this material. Somewhat larger gap values, 2Δmax(c-axis)701 meV, have been also observed at the lateral surface, and these various gap values observed on each surface of the same crystal indicate the characteristic of the large gap anisotropy, Δ()/Δ(//)1.8, of this material.

Experimental results of an N-S junction and analysis of the results using the Arnold theory were reported. Au and Pb were employed as a normal metal and a superconducting material, respectively. The excess current effect due to the Andreev reflection was observed in the current-voltage characteristics of an N-S junction whose normal resistance was 1.603 Ω. The excess current at 4.62 K was about 0.7 mA when the applied voltage was 2 mV. The barrier height and width were estimated to be 1.0169 eV and 0.7 , respectively, by comparing the experimental results and analysis based on the Arnold theory. In the voltage region less than 2 mV, the theory well agreed with the experiment. Moreover, the applied voltage dependence of the supercurrent and quasiparticle current were separately calculated. It was made clear that the supercurrent was larger than the quasiparticle current in the voltage region less than 2Δ/e, where Δ is the superconducting energy gap and e is the absolute value of an electron's charge. The supercurrent began to gradually saturate when the voltage was higher than Δ/e and became constant at the applied voltage greater than 2Δ/e. In our experiment, the excess current larger than expected from the Arnold theory was observed in the voltage region higher than 2Δ/e.

An algorithm interpolating parallel cross-sections between CT slices is described. Contours of equiscalar or constant-density surfaces on cross-sections are directly obtained as non-intersecting loops from grayscale slice images. This algorithm is based on a general algorithm that the authors have proposed earlier, constructing triangulated orientable closed surfaces from grayscale volumes and is particularly suited for a new technique, called laser stereolithography, which creates real 3D plastic objects using UV laser to scan and harden liquid polymer. The process of laser stereolithography is executed slice by slice, and this technique really requires some interpolation of intermediate cross-sections between slices. For visualizing, surfaces are only expected to be shaded almost continuously. The local defects are invisible and not cared about if the picture resolution is rather poor. On the contrary, topological faults are fatal to construct solid models by laser stereolithography, i.e., every contour line on cross-sections must be closed with no intersection. Not a single break of a contour line is tolerated. We already have many algorithms available for equiscalar surface construction, and it seems that if we cut the surfaces, then contour lines could be obtained. However, few of them are directly applicable to solid modeling. Marching cubes algorithm, for example, does not ensure the consistency of surface topology. Our algorithm guarantee an adequate topology of contour lines.

This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.

Current status and critical issues of the material and device technology towards constructing new architecture LSIs based on quantum-mechanical principles are reviewed in an attempt to draw attention of systems workers to the field. Limitations of the present-day LSI architecture are discussed from the viewpoints of material science and device physics. New quantum mechanical phenomena in the quantum structures are reviewed. Then, key material and processing issues for fabrication of desired quantum structures are briefly discussed. Finally, the basic operation principles the quantum devices and possible architectures of quantum LSIs are discussed.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

AlGaAs/GaAs HBT ICs for high bit-rate optical transmission systems, such as preamplifier, D-F/F, differential amplifier, and laser driver, have been newly developed using the hetero guard-ring fully self-aligned HBT (HGFST) fabrication process. In this process, the emitter mesa is ECR-RIBE dry etched using a thick emitter-metal system of WSi and Ti-Pt-Au as etching mask, and a hetero guard-ring composed of a depleted AlGaAs layer is fabricated on p GaAs extrinsic base regions. This process results in highly uniform HBT characteristics. The preamplifier IC exhibits a DC to 18.5-GHz transimpedance bandwidth with a transimpedance gain of 49 dBΩ. The rise time and fall time for the D-F/F IC are 30 and 23 ps, respectively. The laser driver IC has a 40-mAp-p output current swing. The differential amplifier exhibits a DC to 12.1-GHz bandwidth with a 14.2-dB power gain.

The transient spectral spread of directly modulated DFB LD's, which appears in the time-resolved chirping measurement, is studied experimentally and numerically. Such a phenomenon has been already reported as a side mode oscillation called "subpeak", but there has been little argument as to the physical origin. We make it clear that the subpeak is a spurious mode due to the influence of the photodetector bandwidth. The minimum photodetector bandwidth which is necessary in the time-resolved chirping measurement is examined. Furthermore the distortion of the long-distance transmitted waveform is also explained by one mode oscillation.

A new computer architecture using multiwavelength optoelectronic integrated circuits (OEICs) is proposed to attack the problems caused by interconnection complexity. Multiwavelength-OEIC architecures, where various wavelengths are employed as information carriers, provide the wavelength as an extra dimension of freedom for parallel processing, so that we can perform several independent computations in parallel in a single optical module using the wavelength space. This multiplex computing" enables us to reduce the wiring area required by a network and improve their complexity. In this paper, we discuss the efficient multiplexing of Batcher's bitonic sorting networks, highly parallel computing architectures that require global interconnections inherently. A systematic multiplexing of interconnection topology is presented using a binary representation of the connectivities of interconnection paths. It is shown that the wiring area can be reduced by a factor of 1/r2 using r kinds of wavelength components.

We designed and fabricated a prototype 0.4-µm-gate CMOS/SIMOX PLL LSI in order to verify the potential usefulness of ultrathin-film SIMOX technology for creating an extremely low-power LSI containing high-speed circuits operating at frequencies of at least 1 GHz and at low supply voltages. This PLL LSI contains both high-frequency components such a prescaler and low-frequency components such as a shift register, phase frequency comparator, and fixed divider. One application of the LSI could be for synthesizing communication band frequencies in the front-end of a battery-operated wireless handy terminal for personal communications. At a supply voltage of 2 V, this LSI operates at up to 2 GHz while dissipating only 8.4 mW. Even at only 1.2 V, 1 GHz-operation can be obtained with a power consumption of merely 1.4 mW. To explain this low-power feature, we extensively measured the electrical characteristics of individual CMOS/SIMOX basic circuits as well as transistors. Test results showed that the high performance of the LSI is mainly due to the advanced nature of the CMOS/SIMOX devices with low parasitic capacitances around source/drain regions and to the new circuit design techniques used in the dual-modulus prescalar.

The minimum transferable linewidth by X-ray is derived using waveguide analysis. The minimum width is determined by the refractive index of the absorber and does not depend on the X-ray wavelength. Therefore there is an optimum mask aperture size which provides the minimum linewidth. By using Au as the absorber, 8 nm linewidth is attainable.

Selective epitaxial growth technology has been extended to the base formation of a transistor on the basis of the SATURN (Self-Alignment Technology Utilizing Reserved Nitride) process, a high-speed bipolar LSI processing technology. The formation of a self-aligned base contact, coupled with SIC (Selective Ion-implanted Collector) fabricated by lowenergy ion implantation, has not only narrowed the transistor active regions but has drastically reduced the base width. A final base width of 800 and a maximum cut-off frequency of 31 GHz were achieved.

A glass precursor resist (GPR) is designed on the basis of an idea of conversion of organosilicon polymer to an inorganic substance by lithographic procedure. Developed chemical amplification resist system is composed of poly (di-t-butoxysiloxane) and a photoacid generator. It has a high sensitivity of 1.6 µC/cm2, a resolution of 0.2 µm and an extremely high O2-RIE durability compared with bottom resist. Exposed film changed into silicate glass, and it was confirmed by IR spectra.

Practical linewidth measurement accuracy better than 0.02 µm 3 sigma that meets the production requirement for devices with sub-half micron features, was achieved in a field emission scanning electron-beam metrology system (Hitachi S-7000). In order to establish high accuracy linewidth measurement, it was found in the study that reduction of electron-beam diameter and precise control of operating conditions are significantly effective. For the purpose of reducing electron-beam diameter, a novel electron optical system was adopted to minimize the chromatic aberration which defines electron-beam profile. As a result the electron beam diameter was reduced from 20 nm to 16 nm. In order to reduce measurement uncertainties associated with actual operating conditions, a field emission electron gun geometry and an objective lens current monitor were investigated. Then the measurement uncertainties due to operating conditions was reduced from 0.016 µm to 0.004 µm.

Some new circuit configurations for dual-input integrators and differentiators are proposed. The use of a multiplier device around the Operational Amplifier (OA) yields electronic tunability of their time-constant (To) by a Control Voltage (Vx). Experimental results in support of theoretical design and analysis are included.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.